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ADC0802LCN

8-Bit, Microprocessor Compatible, A/D Converters

Intersil 

ADC0802, ADC0803, ADC0804

Input Source Resistance

Large values of source resistance where an input bypass

capacitor is not used will not cause errors since the input

currents settle out prior to the comparison time. If a low-

pass filter is required in the system, use a low-value series

resistor (≤1kΩ) for a passive RC section or add an op amp

RC active low-pass filter. For low-source-resistance

applications (≤1kΩ), a 0.1µF bypass capacitor at the inputs

will minimize EMI due to the series lead inductance of a long

wire. A 100Ω series resistor can be used to isolate this

capacitor (both the R and C are placed outside the feedback

loop) from the output of an op amp, if used.

Stray Pickup

The leads to the analog inputs (pins 6 and 7) should be kept

as short as possible to minimize stray signal pickup (EMI).

Both EMI and undesired digital-clock coupling to these inputs

can cause system errors. The source resistance for these

inputs should, in general, be kept below 5kΩ. Larger values of

source resistance can cause undesired signal pickup. Input

bypass capacitors, placed from the analog inputs to ground,

will eliminate this pickup but can create analog scale errors as

these capacitors will average the transient input switching cur-

rents of the A/D (see Analog Input Current). This scale error

depends on both a large source resistance and the use of an

input bypass capacitor. This error can be compensated by a

full scale adjustment of the A/D (see Full Scale Adjustment)

with the source resistance and input bypass capacitor in

place, and the desired conversion rate.

Reference Voltage Span Adjust

For maximum application flexibility, these A/Ds have been

designed to accommodate a 5V, 2.5V or an adjusted voltage

reference. This has been achieved in the design of the IC as

shown in Figure 12.

Notice that the reference voltage for the IC is either 1/2 of the

voltage which is applied to the V+ supply pin, or is equal to

the voltage which is externally forced at the VREF/2 pin. This

allows for a pseudo-ratiometric voltage reference using, for

the V+ supply, a 5V reference voltage. Alternatively, a volt-

age less than 2.5V can be applied to the VREF/2 input. The

internal gain to the VREF/2 input is 2 to allow this factor of 2

reduction in the reference voltage.

Such an adjusted reference voltage can accommodate a

reduced span or dynamic voltage range of the analog input

voltage. If the analog input voltage were to range from 0.5V to

3.5V, instead of 0V to 5V, the span would be 3V. With 0.5V

applied

voltage

to the

can be

VlN(-)

made

pin to absorb

equal to 1/2 of

the

the

offset, the

3V span or

reference

1.5V. The

A/D now will encode the VlN(+) signal from 0.5V to 3.5V with

the 0.5V input corresponding to zero and the 3.5V input corre-

sponding to full scale. The full 8 bits of resolution are therefore

applied over this reduced analog input voltage range. The req-

uisite connections are shown in Figure 13. For expanded

scale inputs, the circuits of Figures 14 and 15 can be used.

R

VREF/2

9

V+

(VREF) 20

DIGITAL

CIRCUITS

R

DECODE

ANALOG

CIRCUITS

AGND 8

DGND 10

FIGURE 12. THE VREFERENCE DESIGN ON THE IC

VREF

(5V)

ICL7611 5V

FS

“SPAN”/2

-

+

ADJ.

300

0.1µF

TO VREF/2

ZERO SHIFT VOLTAGE

TO VIN(-)

FIGURE 13. OFFSETTING THE ZERO OF THE ADC0802 AND

PERFORMING AN INPUT RANGE (SPAN)

ADJUSTMENT

5V

(VREF)

R

VIN ± 10V

2R

6

20

VIN(+) V+

+

10µF

ADC0802-

2R

ADC0804

7 VIN(-)

FIGURE 14. HANDLING ±10V ANALOG INPUT RANGE

6-14

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