MC100E016 Просмотр технического описания (PDF) - Motorola => Freescale
Номер в каталоге
Компоненты Описание
производитель
MC100E016 Datasheet PDF : 8 Pages
| |||
MC10E016 MC100E016
FUNCTION TABLE
Function PE CE MR TCLD CLK P7-P4 P3 P2 P1 P0 Q7-Q4 Q3 Q2 Q1 Q0 TC
Load
L
X
L
X
Z
H
HH
L
L
H
H
H
L
L
H
Count
H
L
L
L
Z
X
X
X
X
X
H
H
H
L
H
H
H
L
L
L
Z
X
X
X
X
X
H
H
H
H
L
H
H
L
L
L
Z
X
X
X
X
X
H
H
H
H
H
L
H
L
L
L
Z
X
X
X
X
X
L
L
L
L
L
H
Load
L
X
L
X
Z
H
HH
L
L
H
H
H
L
L
H
Hold
H
H
L
X
Z
X
X
X
X
X
H
H
H
L
L
H
H
H
L
X
Z
X
X
X
X
X
H
H
H
L
L
H
Load On
H
L
L
H
Z
H
L
H
H
L
H
H
H
L
H
H
Terminal
H
L
L
H
Z
H
L
H
H
L
H
H
H
H
L
H
Count
H
L
L
H
Z
H
L
H
H
L
H
H
H
H
H
L
H
L
L
H
Z
H
L
H
H
L
H
L
H
H
L
H
H
L
L
H
Z
H
L
H
H
L
H
L
H
H
H
H
H
L
L
H
Z
H
L
H
H
L
H
H
L
L
L
H
Reset
X
X
H
X
X
X
X
X
X
X
L
L
L
L
L
H
Applications Information
Cascading Multiple E016 Devices
For applications which call for larger than 8-bit counters
multiple E016s can be tied together to achieve very wide
bit width counters. The active low terminal count (TC)
output and count enable input (CE) greatly facilitate the
cascading of E016 devices. Two E016s can be cascaded
without the need for external gating, however for counters
wider than 16 bits external OR gates are necessary for
cascade implementations.
Figure 1 below pictorially illustrates the cascading of 4
E016s to build a 32-bit high frequency counter. Note the E101
gates used to OR the terminal count outputs of the lower order
E016s to control the counting operation of the higher order
bits. When the terminal count of the preceding device (or
devices) goes low (the counter reaches an all 1s state) the
more significant E016 is set in its count mode and will count
one binary digit upon the next positive clock transition. In
addition, the preceding devices will also count one bit thus
sending their terminal count outputs back to a high state
disabling the count operation of the more significant counters
and placing them back into hold modes. Therefore, for an
E016 in the chain to count, all of the lower order terminal count
outputs must be in the low state. The bit width of the counter
can be increased or decreased by simply adding or
subtracting E016 devices from Figure 1 and maintaining the
logic pattern illustrated in the same figure.
The maximum frequency of operation for the cascaded
counter chain is set by the propagation delay of the TC output
and the necessary setup time of the CE input and the
propagation delay through the OR gate controlling it (for 16-bit
counters the limitation is only the TC propagation delay and
the CE setup time). Figure 1 shows EL01 gates used to control
the count enable inputs, however, if the frequency of operation
is lower a slower, ECL OR gate can be used. Using the worst
case guarantees for these parameters from the ECLinPS data
book, the maximum count frequency for a greater than 16-bit
counter is 500MHz and that for a 16-bit counter is 625MHz.
LOAD
Q0 –> Q7
Q0 –> Q7
Q0 –> Q7
Q0 –> Q7
LO CE
PE
E016
LSB
CE
PE
E016
CE
PE
E016
CE
PE
E016
MSB
CLK TC
P0 –> P7
CLK TC
EL01
P0 –> P7
CLK TC
EL01
P0 –> P7
CLK TC
P0 –> P7
CLOCK
Figure 1. 32-Bit Cascaded E016 Counter
MOTOROLA
2–4
ECLinPS and ECLinPS Lite
DL140 — Rev 4
Share Link: 