PI6C104H Просмотр технического описания (PDF) - Pericom Semiconductor

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PI6C104H

Spread Spectrum Clock Synthesizer for Desktop Pentium II

Pericom Semiconductor 

PI6C104

Spread Spectrum Clock Synthesizer

for Desktop Pentium II 111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222

Clock Enable Configuration

PD# CPUCLK[0:1] PCICLK[1:5] PCICLK_F Other Clocks Crystal

0

low

low

Running

Running

Running

1

Running

Running

Running

Running

Running

VCO's

Running

Running

PI6C104 I2C Address Assignment 0D2H

A7 A6 A5 A4 A3 A2 A1 A0

1

1

0

1

0

0

1

0

Frequency Table

S0 S1 S2 CPU PCI

0

0

0

75

30

0

0

1 66.8 33.4

0

1

0 66.6 33.3

0

1

1 66.8 33.4

1

0

0

112 37.3

1

0

1 83.3 33.3

1

1

0

100 33.3

1

1

1 100 33.3

2-Wire I2C Control

The I2C interface permits individual enable/disable of each clock

output and test mode enable.

The PI6C104 is a slave receiver device. It can not be read back. Sub

addressing is not supported. All preceding bytes must be sent in

order to change one of the control bytes.

Every byte put on the SDATA line must be 8-bits long (MSB first),

followed by an acknowledge bit generated by the receiving device.

During normal data transfers SDATA changes only when SCLK is

LOW. Exceptions: A HIGH to LOW transition on SDATA while

SCLK is HIGH indicates a “start” condition. A LOW to HIGH

transition on SDATA while SCLK is HIGH is a “stop” condition

and indicates the end of a data transfer cycle.

Each data transfer is initiated with a start condition and ended

with a stop condition. The first byte after a start condition is always

a 7-bit address byte followed by a read/write bit. (HIGH = read

from addressed device, LOW = write to addressed device).

If the device’s own address is detected, PI6C104 generates an

acknowledge by pulling SDATA line LOW during ninth clock

pulse, then accepts the following data bytes until another start or

stop condition is detected.

Following acknowledgement of the address byte (D2), two more

bytes must be sent:

1. “Command Code” byte, and

2. “Byte Count” byte.

Although the data bits on these two bytes are “don’t care,” they

must be sent and acknowledged.

236

PS8164B 03/15/99

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