DELIC-LC Просмотр технического описания (PDF) - Infineon Technologies
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DELIC-LC Datasheet PDF : 8 Pages
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PEB 20570/PEF 20570
PEB 20571/PEF 20571
DELIC Strap Option Configuration
4
DELIC Strap Option Configuration
The DELIC “Strap Status Register (CSTRAP)” is described in the DELIC-LC PEB
20570/DELIC-PB PEB 20571 Data Sheet, independent of the version (2.1 .. 3.1). The
register description (see updated register CSTRAP) of the Data Sheet is misleading
concerning bit 0 and 1. They are not configured by strap option. For a stable DCXO
synchronization it is recommended to proceed as follows:
1. After Boot read register CSTRAP to detect the value
2. Set only bit CSTRAP:DCXO to ’0’ and set the others as detected before
CSTRAP
Strap Status Register
15
14
13
(D08FH) Reset Value: 0000 0xxx xxxx xx10B
12
11
10
9
8
Res
STRAP
rw
rw
7
6
5
4
3
2
1
0
STRAP
rw
DCXO
rw
ISCD
rw
Field
Res
STRAP
DCXO
Bits Type Description
[15:11] rw
Reserved
Returns 0 upon read; must be written with 0.
[10:2] rw
STRAP Pin Definition
This register enables the OAK® to read the strap values
sampled during reset.
Bit Function
10 PCM Clock Master Strap
9:7 Test Mode Strap
6 Emulation Boot Strap
5 PLL Bypass Strap
4 DSP PLL Power-Down Strap
3 Boot Strap
2 Reset counter Bypass Strap
1
rw DCXO Synchronization Config
0 Linear (slow) synchronization
1 Fast synchronization (default)
Addendum
7/8
2003-08-04
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