DELIC-LC Просмотр технического описания (PDF) - Infineon Technologies

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DELIC-LC

2 Channel Serial Optimized Communication Controller for HDLC/PPP

Infineon Technologies 

PEB 20570/PEF 20570

PEB 20571/PEF 20571

Addendum to “DELIC Clock System Synchronization”

The time within the DELIC DCXO guarantees the 100 ppm clock accuracy varies,

depending on various conditions. When the central office deactivates, the user will be

notified by the DELIC. It is up to the user to provide another clock source (for example

REFCLK) for the DCXO as soon as possible.

1.2

VIP clocked in LT-T Mode by an external Crystal

16.384 M Hz

C e n tra l

O ffice

15.36 M Hz

OSC

/10

RxPLL

DCXO

8kHz

16.384 MHz PD

PLL

Divider M UX

Divider DELIC Divider

REFCLK

XCLK

VIP

1.536 M Hz

Mux REFCLK

D E L IC _ re fclk2

Figure 2 Clocking the VIP by using external Crystal

As shown in Figure 2 no unstable system can occur by using an external crystal rather

than the DELIC Layer 1 clock as VIP clock source in LT-T mode. When the central office

line is deactivated, the VIP takes the 15.36 MHz oscillator signal and divides it by 10.

This signal is used as XCLK input of the DELIC DCXO. Since the VIP 15.36 MHz signal

is entirely independent from the DELIC clocking system no unstable system can occur.

Note: In LT-T mode it is recommended to use an external crystal to clock the VIP.

Addendum

3/8

2003-08-04

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