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PEEL16CV8J-25 Просмотр технического описания (PDF) - Anachip Corporation

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производитель
PEEL16CV8J-25 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
A. C. Electrical Characteristics
Over the Operating Range 8, 11
Symbol
tPD
tOE
tOD
tCO1
tCO2
tCF
tSC
tHC
tCL, tCH
tCP
fMAX1
fMAX2
fMAX3
tAW
tAP
tAR
tRESET
Parameter
Input5 to non-registered output
Input5 to output enable6
Input5 to output disable6
Clock to Output
Clock to comb. Output delay
Via internal registered feedback
Clock to Feedback
Input5 or feedback setup to clock
Input5 hold after clock
Clock low time, clock high time8
Min clock period Ext (tSC + tCO1)
Internal feedback (1/tSC +tCF)11
External Feedback (1/tCP)11
No Feedback (1/tCL +tCH)11
Asynchronous Reset Pulse Width
Input5 to Asynchronous Reset
Asynchronous Reset recovery time
Power-on reset time for registers in clear
state
Min
Max Unit
25
ns
25
ns
25
ns
15
ns
35
ns
10
ns
20
ns
0
ns
15
ns
35
ns
28.5
MHz
28.5
MHz
33.3
MHz
25
ns
25
ns
25
ns
5
µs
Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Notes:
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for periods less than
20 ns.
2. VI and VO are not specified for program/verify operation.
3. Test Points for Clock and VCC in tR and tF are referenced at the 10% and 90% levels.
4. I/O pins are 0V and VCC.
5. “Input” refers to an input pin signal.
6. tOE is measured from input transition to VREF±0.1V, TOD is measured from input transi- tion
to VOH-0.1V or VOL+0.1V; VREF=VL.
7. Capacitances are tested on a sample basis.
8. Test conditions assume: signal transition times of 3ns or less from the 10% and 90%
points, timing reference levels of 1.5V (Unless otherwise specified).
9. Test one output at a time for a duration of less than 1 second.
10. ICC for a typical application: This parameter is tested with the device programmed as an
8-bit Counter.
11. Parameters are not 100% tested. Specifications are based on initial characterization and
are tested after any design process modification that might affect operational fre- quency.
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
9/11

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