PEB20542 Просмотр технического описания (PDF) - Infineon Technologies

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PEB20542

2 Channel Serial Optimized Communication Controller with DMA

Infineon Technologies 

PEB 20542

PEF 20542

Introduction

1

Introduction

The SEROCCO-D is a DMA Integrated Serial Communication Controller with two

independent serial channels1). The serial channels are derived from updated protocol

logic of the ESCC and DSCC4 device family providing a large set of protocol support and

variety in serial interface configuration. This allows easy integration to different

environments and applications.

A generic 8- or 16-bit demultiplexed master/slave interface provides fast device access

with low bus utilization and easy software handshaking. The internal DMA controller is

optimized for a minimum CPU intervention. Different control mechanisms allow easy

software development well adapted to the needs of special applications (e.g. frame/

packet oriented and continuous transmission/reception).

Large on-chip FIFOs of 64 byte capacity per port and direction in combination with

enhanced threshold control mechanisms allow decoupling of traffic requirements on host

bus and serial interfaces with little exception probabilities such as data underruns or

overflows.

Each of the two Serial Communication Controllers (SCC) contains an independent Baud

Rate Generator, DPLL and programmable protocol processing (HDLC, PPP, ASYNC

and BISYNC). Data rates of up to 16 Mbit/s (HDLC, PPP, bit transparent) and 2 Mbit/s

(DPLL assisted modes) are supported. The channels can also handle a large set of

layer-2 protocol functions (LAPD, SS7) reducing bus and host CPU load. Two channel

specific timers are provided to support protocol functions.

1) The serial channels are also called ’ports’ or ’cores’ depending on the context.

Data Sheet

18

2000-09-14

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