PEB20542 Просмотр технического описания (PDF) - Infineon Technologies

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PEB20542

2 Channel Serial Optimized Communication Controller with DMA

Infineon Technologies 

• Protocol and Mode Independent

– Data bit inversion

– Data overflow and underrun detection

– Timer

PEB 20542

PEF 20542

Introduction

Protocol Support

• Address Recognition Modes

– No address recognition (Address Mode 0)

– 8-bit (high byte) address recognition (Address Mode 1)

– 8-bit (low byte) or 16-bit (high and low byte) address recognition (Address Mode 2)

• HDLC Automode

– 8-bit or 16-bit address generation/recognition

– Support of LAPB/LAPD

– Automatic handling of S- and I-frames

– Automatic processing of control byte(s)

– Modulo-8 or modulo-128 operation

– Programmable time-out and retry conditions

– SDLC Normal Response Mode (NRM) operation for slave

• Signaling System #7 (SS7) support

– Detection of FISUs, MSUs and LSSUs

– Unchanged Fill-In Signaling Units (FISUs) not forwarded

– Automatic generation of FISUs in transmit direction (incl. sequence number)

– Counting of errored signaling units

Integrated DMA Controller

• 4 independent DMA channels

• Optimized for minimum CPU intervention

• Efficient block-oriented data transfer

• Bus preemption

• Fragmented transmission/reception of data packets from/into multiple buffers

• Switched-Buffer mode for seamless update of buffer base address and size

• 24-bit adressable memory range

• Optional DTACK/READY controlled cycles

Microprocessor Interface

• 8/16-bit bus interface

• De-multiplexed address/data bus

• Intel/Motorola style

• Asynchronous interface

• Maskable interrupts for each channel

Data Sheet

21

2000-09-14

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