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HT48RA0A

8-Bit Remote Type MCU

Holtek Semiconductor 

HT48RA0A

Carrier

The HT48RA0A provides a carrier output which shares

the pin with PC0. It can be selected to be a carrier output

(REM) or level output pin (PC0) by code option. If the

carrier output option is selected, setting PC0=²0² to en-

able carrier output and setting PC0=²1² to disable it at

low level output.

The clock source of the carrier is implemented by in-

struction clock (system clock divided by 4) and pro-

cessed by a frequency divider to yield various carry

frequency.

Clock Source

Carry Frequency=

m´2n

where m=2 or 3 and n=0~3, both are selected by code

option. If m=2, the duty cycle of the carrier output is 1/2

duty. If m=3, the duty cycle of the carrier output can be

1/2 duty or 1/3 duty also determined by code option (with

the exception of n=0).

Detailed selection of the carrier duty is shown below:

m´2n

Duty Cycle

2, 4, 8, 16

1/2

3

1/3

6, 12, 24

1/2 or 1/3

The following table shows examples of carrier fre-

quency selection.

fSYS

fCARRIER

Duty

m´2n

37.92kHz

1/3 only

3

455kHz

56.9kHz

1/2 only

2

Input/Output Ports

There are an 8-bit bidirectional input/output port, a 6-bit

input with 2-bit I/O port and one-bit output port in the

HT48RA0A, labeled PA, PB and PC which are mapped to

[12H], [14H], [16H] of the RAM, respectively. Each bit of

PA can be selected as NMOS output or Schmitt trigger

with pull-high resistor by software instruction. PB0~PB1

have the same structure with PA, while PB2~PB7 can

only be used for input operation (Schmitt trigger with

pull-high resistors). PC is only one-bit output port shares

the pin with carrier output. If the level option is selected,

the PC is CMOS output.

Both PA and PB for the input operation, these ports are

non-latched, that is, the inputs should be ready at the T2

rising edge of the instruction ²MOV A, [m]² (m=12H or

14H). For PA, PB0~PB1 and PC output operation, all

data are latched and remain unchanged until the output

latch is rewritten.

When the PA and PB0~PB1 is used for input operation,

it should be noted that before reading data from pads, a

²1² should be written to the related bits to disable the

NMOS device. That is, the instruction ²SET [m].i² (i=0~7

for PA, i=0~1 for PB) is executed first to disable related

NMOS device, and then ²MOV A, [m]² to get stable data.

After chip reset, PA and PB remain at a high level input

line while PC remain at high level output, if the level op-

tion is selected.

Each bit of PA, PB0~PB1 and PC output latches can be

set or cleared by the ²SET [m].i² and ²CLR [m].i²

(m=12H, 14H or 16H) instructions respectively.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR [m]²,

²CPL [m]², ²CPLA [m]² read the entire port states into

the CPU, execute the defined operations (bit-operation),

and then write the results back to the latches or to the

accumulator.

Each line of PB has a wake-up capability to the device

by code option. The highest seven bits of PC are not

physically implemented, on reading them a ²0² is re-

turned and writing results in a no-operation.

C lo c k S o u r c e

( S y s te m C lo c k /4 )

F r e q u e n c y D iv id e r

3 - b it C o u n te r

C o d e O p tio n

V DD

1 /2 o r 1 /3 d u ty

Level

1 /2

C a r r ie r D u ty

S e le c t

1 /3

C a r r ie r

R e a d p a th fo r r e a d - m o d ify - w r ite

C o d e O p tio n

( c a r r ie r o r le v e l)

C a r r ie r

Level

P C 0 D a ta R e g is te r

R E M /P C 0

Carrier/Level output

Rev. 1.70

9

July 16, 2003

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