PCD3354AH Просмотр технического описания (PDF) - Philips Electronics

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PCD3354AH

8-bit microcontrollers with DTMF generator and 256 bytes EEPROM

Philips Electronics 

Philips Semiconductors

8-bit microcontrollers with DTMF

generator and 256 bytes EEPROM

Product specification

PCA3354C; PCD3354A

handbook, full pagewidth

fxtal

8

CLOCK AND MELODY

CONTROL REGISTER

8

HGF REGISTER

8 INTERNAL BUS

8

LGF REGISTER

CLOCK

DIVIDER

fDTMF

PORT/CLOCK

OUTPUT LOGIC

DP1.7/

DCO

DIGITAL

SINE WAVE

SYNTHESIZER

SWITCHED

CAPACITOR

BANDGAP

VOLTAGE

REFERENCE

DIGITAL

SINE WAVE

SYNTHESIZER

square wave

DAC

DAC

SWITCHED

CAPACITOR

LOW-PASS

FILTER

PORT/MELODY

OUTPUT LOGIC

P1.7/

MDY

RC LOW-PASS

FILTER

MGB782

TONE

Fig.3 Block diagram of the frequency generator, melody output (P1.7/MDY) and DTMF clock output (DP1.7/DCO).

6.2 Melody output (P1.7/MDY)

The melody output (P1.7/MDY) is very useful for

generating musical notes when a purely sinusoidal signal

is not required, such as for ringer applications.

The square wave (duty cycle = 12⁄23 or 52%) will include

the attenuated harmonics of the base frequency, which is

defined by the contents of the HGF register (Table 3).

However, even higher frequency notes may be produced

since the low-pass filtering on the TONE output is not

applied to the P1.7/MDY output. This results in the

minimum decimal value x in the HGF register (see

equation in Section 6.4) being 2 for the P1.7/MDY output,

rather than 60 for the TONE output. A sinusoidal TONE

output is produced at the same time as the melody square

wave, but due to the filtering, the higher frequency sine

waves with x < 60 will not appear at the TONE output.

Since the melody output is shared with P1.7, the port

flip-flop of P1.7 has to be set HIGH before using the

melody output. This is to avoid conflicts between melody

and port outputs. The melody output drive depends on the

configuration of port P1.7/MDY, see Chapter 13, Table 24.

6.3 DTMF clock divider and output (DP1.7/DCO)

The DTMF clock divider allows the DTMF part to run either

with the main clock frequency (fDTMF = fxtal) or with a third

of it (fDTMF = 1⁄3 × fxtal) depending on the state of the divider

control bit DIV3 in register MDYCON.

For low power applications, a 3.58 MHz quartz crystal or

PXE resonator can be chosen together with the

divide-by-one function of the clock divider.

For other applications a 10.74 MHz quartz crystal or PXE

resonator may be chosen together with the divide-by-three

function of the clock divider. This triples the program speed

of the microcontroller, thereby keeping the assumed

DTMF frequency of 3.58 MHz.

Since a 3.58 MHz clock is needed for peripheral telephony

circuits such as the analog voice scrambler/descrambler

PCD4440T, a switchable DTMF clock output is provided

depending on the state of the enable clock output bit

EDCO in register MDYCON.

1996 Dec 18

8

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