ICS1889Y Просмотр технического описания (PDF) - Integrated Circuit Systems

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ICS1889Y

100Base-FX Integrated PHYceiver™

Integrated Circuit Systems 

ICS1889

Block Diagram

Functional Description

Introduction

The ICS1889 is a nibble to bit stream and bit stream to nibble

processor. When transmitting, it takes sequential nibbles

presented at the Media Independent Interface (MII) and

translates them to a serial bit stream for transmission on the

media. When receiving, it takes the serial bit stream from the

media and translates it to sequential nibbles for presentation

to the MII. It has no knowledge of the underlying structure of

the MAC frame it is conveying.

When transmitting, the ICS1889 encapsulates the MAC

frame (including the preamble) with the start-of-stream

(SSD) and end-of-stream (ESD) delimiters. When receiving,

it strips off the SSD and substitutes the normal preamble

pattern and then presents this and subsequent preamble

nibbles to the MII. When it encounters the ESD it ends the

presentation of nibbles to the MII. Thus, the MAC

reconciliation layer sees an exact copy of the transmitted

frame.

During periods when no frames are being transmitted or

received, there is a requirement to signal and detect the idle

condition. This allows the higher levels to determine the

integrity of the connection between the node and the hub. A

continuous stream of ones is transmitted to signify the idle

condition, the receive channel includes logic that monitors

the IDLE data stream to look for this pattern and thereby

establish the link integrity.

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