ICS1889Y Просмотр технического описания (PDF) - Integrated Circuit Systems

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ICS1889Y

100Base-FX Integrated PHYceiver™

Integrated Circuit Systems 

ICS1889

Receive Error (RXER)

The ICS1889 detects two types of receive errors, errors

occurring during the reception of valid frames and an error

condition known as false carrier detect. False carrier detect is

signaled so that repeater applications can prevent the

propagation of false carrier detection. RXER always

transitions synchronously with RXCLK.

The assertion of Receive Error (RXER) for one or more clock

periods during the period when RXDV is asserted (receiving

a frame) indicates that the ICS1889 has detected a read

channel error. There are three sources of read channel error

loss of receive signal, failure of the PLL to lock and invalid

symbol detection (including the HALT symbol). Timing

diagram xxx (RXER Timing Diagram) shows the relationship

of RXER to RXCLK, RXEN and receive channel error

conditions.

RXER may also be asserted when RXDV is de-asserted. The

ICS1889 will assert RXER and set RXD(3:0) to 1110 if a

false carrier is detected. For a good carrier to be detected, the

ICS1889 looks continuously at the incoming IDLE stream

(1111...) for two non-contiguous logic zeros and then checks

for the SSD of “JK.” In the event that two non-contiguous

logic zeroes are detected but the JK symbol pair is not, then a

false carrier condition is signaled and the IDLE condition is

reentered.

Carrier Sense (CRS)

The ICS1889 asserts Carrier Sense (CRS) when it detects that

receive channel is non-idle in the full duplex mode or when it

detects that either the receive or transmit channels are non-

idle in the half duplex mode. A receive channel non-idle

condition is detected by two non-contiguous zeros in any 10

bits (“IJ”). CRS is not synchronous to either the transmit or

receive clocks.

Collision Detected (COL)

The ICS1889 asserts Collision Detected (COL) when it

detects a receive carrier (non-idle) condition while

transmitting (TXEN asserted) in the half duplex mode. The

COL is not synchronous to either the transmit or receive

clocks. In full duplex mode, collision will be disabled.

Management Data Clock (MDC)

The Management Data Clock (MDC) is used by the ICS1889

to synchronize the transfer of management information to or

from the ICS1889. The ICS1889 requires minimum high and

low times of 160 ns and a minimum clock period of 400 ns.

Management Data Input/Output

The Management Data Input/Output (MDIO) is a tristate line

driven by station management to transfer command

information or driven by the ICS1889 to transfer status

information. All transfers and sampling are synchronous with

MDC. If the ICS1889 is to be used in an application which

uses the mechanical MII specification, MDIO must have a

pull-up at the ICS1889 end and a pull-down at the station

management end. This enables station management to

determine if the connection is intact.

Transmit and Receive Pin Descriptions

Transmit Pair (TX+ & TX-)

The Transmit pair TX+ and TX- carries the NRZI serial bit

stream for conversion to optical signals.

Receive Pair (RX+ & RX-)

The Receive pair RX+ and RX- carries the NRZI serial bit

stream from the optical converter.

Transmit Current Program (IPRG)

This pin is connected to a resistor and sets the current drive of

the transmitter.

Frequency Reference (REF_IN and REF_OUT)

A 25 MHz crystal oscillator or reference source should be fed

into the REF_IN input, while leaving REF-OUT not

connected.

Signal Detect (SD+ & SD-)

This PECL input pair provides a signal detect indication from

the optical transceiver. The ICS1889 will indicate a receive

channel error if this signal is de-asserted. A receive channel

error is also indicated if either a PLL lock error or a receive

signal error is detected.

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