ICS1889Y Просмотр технического описания (PDF) - Integrated Circuit Systems

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Компоненты Описание

производитель

ICS1889Y

100Base-FX Integrated PHYceiver™

Integrated Circuit Systems 

ICS1889

Pin Definitions

Signal

TXCLK

TXEN

TXD3

TXD2

TXD1

TXD0

TXER

RXCLK

RXDV

RXD3

RXD2

RXD1

RXD0

RXER

CRS

COL

MDC

MDIO

Meaning

Transmit Clock

Transmit Enable

Transmit Data 3

Transmit Data 2

Transmit Data 1

Transmit Data 0

Transmit Error

Receive Clock

Receive Data Valid

Receive Data 3

Receive Data 2

Receive Data 1

Receive Data 0

Receive Error

Carrier Sense

Collision Detect

Management Data Clock

Management Data Input/Output

Signal

TX+

TX–

IPRG

RX+

RX–

REF+

REF–

SD+

SD–

Meaning

Transmitted data positive

Transmitted Data negative

Current program

Receive Data positive

Receive Data negative

Frequency reference

Frequency reference

Signal Detect

Signal Detect

SYSR

PRIO

DPEN

LSTA

P4RD

P3TD

P2LI

P1CL

P0FD

NOD/REP

System reset

Priority

Duplex Enable

Link Status

Receive data LED

Transmit data LED

Link Integrity LED

Collision detect LED

Full duplex LED

Node or Repeater Mode Selection

MII Interface Pin Descriptions

Transmit Clock TXCLK

The Transmit Clock (TXCLK) is a continuous clock signal

generated by the ICS1889 to synchronize the Transmit

Enable, Transmit Data and Transmit Error lines. The

ICS1889 clock frequency is 25% of the nominal transmit data

rate. At 100 Mbps its frequency is 25 MHz. The TXCLK

clock duty cycle is in the range 35% to 65%.

Transmit Enable TXEN

Transmit Enable (TXEN) indicates to the ICS1889 that the

MAC is sending valid data nibbles for transmission on the

physical media. Synchronous with its assertion the ICS1889

will begin reading the data nibbles on the transmit data lines.

It is the responsibility of the MAC to order the nibbles so that

the preamble is sent first, followed by destination, source,

length, data and CFS fields since the ICS1889 has no

knowledge of the frame structure and is merely a “nibble”

processor. The ICS1889 terminates transmission of nibbles

following the deassertion of Transmit Enable (TXEN).

Transmit Data 3 TXD3

Transmit Data 3 (TXD3) is the most significant bit of the

transmit data nibble. TXD3 is sampled by the ICS1889

synchronously with the Transmit Data Clock when TXEN is

asserted. When TXEN is de-asserted the ICS1889 is

unaffected by the state of TXD3

Transmit Data 2 TXD2

Transmit Data 2 (TXD2) is sampled by the ICS1889

synchronously with the Transmit Data Clock when TXEN is

asserted. When TXEN is de-asserted the ICS1889 is

unaffected by the state of TXD2.

Transmit Data 1 TXD1

Transmit Data 1 (TXD1) is sampled by the ICS1889

synchronously with the Transmit Data Clock when TXEN is

asserted. When TXEN is de-asserted the ICS1889 is

unaffected by the state of TXD1.

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