PCK953BD Просмотр технического описания (PDF) - NXP Semiconductors.
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PCK953BD Datasheet PDF : 15 Pages
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NXP Semiconductors
PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
9. Dynamic characteristics
Table 6. Dynamic characteristics
Tamb = 0 °C to 70 °C; VCC = 3.3 V ± 5 %; unless specified otherwise.
Symbol Parameter
Conditions
tr(o)
tf(o)
δo
tsk(o)
fVCO
fo(max)
output rise time
output fall time
output duty cycle
output skew time
PLL VCO lock range
maximum output frequency
0.8 V to 2.0 V
0.8 V to 2.0 V
output-to-output; relative to QFB
PLL mode; VCO_SEL = 1
PLL mode; VCO_SEL = 0
Bypass mode
tpd(lock)
input to EXT_FB delay (with
PLL locked)
fref = 50 MHz
tpd(bypass)
tPLZ-HZ
tPZL
tjit(cc)
tlock
input to Qn delay
output disable time
output enable time
cycle-to-cycle jitter time
maximum PLL lock time
PLL bypassed
peak-to-peak
10. PLL input reference characteristics
Min
Typ
Max Unit
0.30 0.55 0.8
ns
0.30 0.55 0.8
ns
45
50
55
%
-
-
100
ps
120
-
500
MHz
20
-
100
MHz
35
-
125
MHz
-
-
225
MHz
−75
-
+125 ps
3
5.2
7
ns
-
-
7
ns
-
-
6
ns
-
55
100
ps
-
0.01 10
ms
Table 7. PLL input reference characteristics
Tamb = 0 °C to 70 °C.
Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
Symbol Parameter
Conditions
Min
Typ
Max Unit
fref
frefDC
reference input frequency
reference input duty cycle
20
-
25
-
125
MHz
75
%
PCK953_5
Product data sheet
Rev. 05 — 9 October 2008
© NXP B.V. 2008. All rights reserved.
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