PCK953BD Просмотр технического описания (PDF) - NXP Semiconductors.
Номер в каталоге
Компоненты Описание
производитель
PCK953BD Datasheet PDF : 15 Pages
| |||
NXP Semiconductors
PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VCC
supply voltage
−0.3
VI
input voltage
−0.3
II
input current
-
Tstg
storage temperature
−40
Max
Unit
+4.6
V
VDD + 0.3 V
±20
mA
+125
°C
8. Static characteristics
Table 5. Static characteristics
Tamb = 0 °C to 70 °C; VCC = 3.3 V ± 5 %, unless specified otherwise.
Symbol Parameter
Conditions
VIH
HIGH-level input voltage
LVCMOS inputs
VIL
LOW-level input voltage
LVCMOS inputs
Vi(p-p)
peak-to-peak input voltage
PECL_CLK
Vcm
common-mode voltage
VOH
HIGH-level output voltage
PECL_CLK
IOH = −20 mA
VOL
LOW-level output voltage
IOL = 20 mA
II
input current
Ci
input capacitance
CPD
power dissipation capacitance
per output
ICC
maximum quiescent supply current all VCC pins
ICCPLL
maximum PLL supply current
VCCA pin only
Min
Typ
2.0
-
-
-
300
-
[1] VCC − 1.5 -
[2] 2.4
-
[2] -
-
-
-
-
-
-
25
-
9
-
9
Max
Unit
3.6
V
0.8
V
1000
mV
VCC − 0.6 mV
-
V
0.5
V
±75
µA
4
pF
-
pF
20
mA
20
mA
[1] Vcm is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is
within the Vcm range and the input swing lies within the Vi(p-p) specification.
[2] The PCK953 outputs can drive series or parallel terminated 50 Ω (or 50 Ω to 0.5VCC) transmission lines on the incident edge (see
Section 11 “Application information”).
PCK953_5
Product data sheet
Rev. 05 — 9 October 2008
© NXP B.V. 2008. All rights reserved.
4 of 15
Share Link: 