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PC8576C-1 Просмотр технического описания (PDF) - NXP Semiconductors.

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PC8576C-1
NXP
NXP Semiconductors. NXP
PC8576C-1 Datasheet PDF : 57 Pages
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NXP Semiconductors
PCF8576C
Universal LCD driver for low multiplex rates
VDD
R
tr
2CB
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
OSC
VDD
VLCD
PCF8576C
40 segment drives LCD PANEL
4 backplanes
(up to 160
elements)
A0 A1 A2 SA0 VSS
013aaa098
VSS
Fig 7. Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication
channel with the PCF8576C.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (pins VDD, VSS, and VLCD) and the LCD panel selected for the application.
7.1 Power-On-Reset (POR)
At power-on the PCF8576C resets to the following starting conditions:
All backplane and segment outputs are set to VDD
The selected drive mode is 1:4 multiplex with 13 bias
Blinking is switched off
Input and output bank selectors are reset (as defined in Table 8)
The I2C-bus interface is initialized
The data pointer and the subaddress counter are cleared
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
The full-scale LCD voltage (Voper) is obtained from VDD VLCD. The LCD voltage may be
temperature compensated externally through the VLCD supply to pin VLCD.
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising
three series resistors connected between VDD and VLCD. The center resistor can be
switched out of the circuit to provide a 12 bias voltage level for the 1:2 multiplex
configuration.
PCF8576C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 22 July 2010
© NXP B.V. 2010. All rights reserved.
10 of 57

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