PCF8564AU/5BB/1 Просмотр технического описания (PDF) - NXP Semiconductors.
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PCF8564AU/5BB/1 Datasheet PDF : 48 Pages
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NXP Semiconductors
PCF8564A
Real time clock and calendar
Table 27. First increment of time circuits after STOP bit release
Bit
Prescaler bits
[1] 1 Hz tick Time
Comment
STOP F0F1-F2 to F14
Clock is running normally
hh:mm:ss
0
01-0 0001 1101 0100
12:45:12
prescaler counting normally
STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally
1
XX-0 0000 0000 0000
12:45:12
prescaler is reset; time circuits are frozen
New time is set by user
1
XX-0 0000 0000 0000
08:00:00
prescaler is reset; time circuits are frozen
STOP bit is released by user
0
XX-0 0000 0000 0000
08:00:00
prescaler is now running
XX-1 0000 0000 0000
08:00:00
-
XX-0 1000 0000 0000
08:00:00
-
XX-1 1000 0000 0000
08:00:00
-
:
:
:
11-1 1111 1111 1110
08:00:00
-
00-0 0000 0000 0001
10-0 0000 0000 0001
08:00:01
08:00:01
0 to 1 transition of F14 increments the time circuits
-
:
:
:
11-1 1111 1111 1111
08:00:01
-
00-0 0000 0000 0000
08:00:01
-
10-0 0000 0000 0000
08:00:01
-
:
:
-
11-1 1111 1111 1110
08:00:01
-
00-0 0000 0000 0001
08:00:02
0 to 1 transition of F14 increments the time circuits
DDD
[1] F0 is clocked at 32.768 kHz.
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP
bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset
(see Table 27) and the unknown state of the 32 kHz clock.
8.11 Reset
The PCF8564A includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I2C-bus logic is initialized including the address pointer and
all registers are set according to Table 28. I2C-bus communication is not possible during
reset.
PCF8564A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 26 August 2013
© NXP B.V. 2013. All rights reserved.
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