PCF8564AU/5BB/1 Просмотр технического описания (PDF) - NXP Semiconductors.

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PCF8564AU/5BB/1

Real time clock and calendar

NXP Semiconductors. 

NXP Semiconductors

PCF8564A

Real time clock and calendar

8.8.2 Register Timer

Table 25. Timer - timer register (address 0Fh) bit description

Bit Symbol

Value

Description

7 to 0 TV[7:0]

0h to FFh countdown timer value[1]

[1] Countdown period in seconds: CountdownPeriod = ----------------------------T----V------------------------------ where TV is the

SourceClockFrequency

countdown timer value.

Table 26. Timer register bits value range

Bit

7

6

5

4

3

2

1

0

128

64

32

16

8

4

2

1

The timer register is an 8-bit binary countdown timer. It is enabled or disabled via the timer

control register. The source clock for the timer is also selected by the timer control

register. Other timer properties such as single or periodic interrupt generation are

controlled via the register Control_2 (address 01h).

For accurate read back of the count down value, the I2C-bus clock (SDA) must be

operating at a frequency of at least twice the selected timer clock. Since it is not possible

to freeze the countdown timer counter during read back, it is recommended to read the

register twice and check for consistent results.

8.9 EXT_CLK test mode

The test mode is entered by setting the TEST1 bit of register Control_1 to logic 1. The

CLKOUT pin then becomes an input. The test mode replaces the internal 64 Hz signal

with that applied to the CLKOUT pin. Every 64 positive edges applied to CLKOUT then

generates an increment of one second.

The signal applied to the CLKOUT pin should have a minimum pulse width of 300 ns and

a maximum period of 1000 ns. The 64 Hz clock, now sourced from CLKOUT, is divided

down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set to a known

state by using the STOP bit. When the STOP bit is set, the prescaler is reset to logic 0.

(STOP must be cleared before the prescaler can operate.)

From a STOP condition, the first 1 second increment will take place after 32 positive

edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment.

Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.

When entering the test mode, no assumption as to the state of the prescaler can be made.

8.9.1 Operation example

1. Set EXT_CLK test mode (Bit 7 Control_1 = 1).

2. Set STOP (Bit 5 Control_1 = 1).

3. Clear STOP (Bit 5 Control_1 = 0).

4. Set time registers to desired value.

5. Apply 32 clock pulses to CLKOUT.

PCF8564A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 26 August 2013

© NXP B.V. 2013. All rights reserved.

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