PCF8563T/5 Просмотр технического описания (PDF) - NXP Semiconductors.
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PCF8563T/5 Datasheet PDF : 45 Pages
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NXP Semiconductors
PCF8563
Real-time clock/calendar
8.3 Control registers
8.3.1 Register Control_status_1
Table 5.
Bit
7
6
5
4
3
2 to 0
Control_status_1 - control and status register 1 (address 00h) bit description
Symbol Value Description
Reference
TEST1 0[1]
normal mode
Section 8.9
must be set to logic 0 during normal operations
1
EXT_CLK test mode
N
0[2]
unused
STOP
0[1]
RTC source clock runs
Section 8.10
1
all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC
clock is stopped (CLKOUT at 32.768 kHz is still available)
N
0[2]
unused
TESTC 0
Power-On Reset (POR) override facility is disabled; set to logic 0 for
normal operation
Section 8.11.1
1[1]
Power-On Reset (POR) override may be enabled
N
000[2] unused
[1] Default value.
[2] Bits labeled as N should always be written with logic 0.
8.3.2 Register Control_status_2
Table 6. Control_status_2 - control and status register 2 (address 01h) bit description
Bit
Symbol Value
Description
7 to 5 N
000[1]
unused
4
TI_TP
0[2]
INT is active when TF is active (subject to the status of TIE)
1
INT pulses active according to Table 7 (subject to the status of TIE);
Remark: note that if AF and AIE are active then INT will be
permanently active
3
AF
0[2]
read: alarm flag inactive
write: alarm flag is cleared
1
read: alarm flag active
write: alarm flag remains unchanged
2
TF
0[2]
read: timer flag inactive
write: timer flag is cleared
1
read: timer flag active
write: timer flag remains unchanged
1
AIE
0[2]
alarm interrupt disabled
1
alarm interrupt enabled
0
TIE
0[2]
timer interrupt disabled
1
timer interrupt enabled
[1] Bits labeled as N should always be written with logic 0.
[2] Default value.
Reference
Section 8.3.2.1
and
Section 8.8
Section 8.3.2.1
PCF8563
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 16 June 2011
© NXP B.V. 2011. All rights reserved.
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