PCF2119AU/2DA/2 Просмотр технического описания (PDF) - NXP Semiconductors.
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PCF2119AU/2DA/2 Datasheet PDF : 83 Pages
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NXP Semiconductors
PCF2119x
LCD controllers/drivers
Table 4. State after reset
Step Function
1
Clear_display
2
Entry_mode_set
3
Display_ctl
4
Function_set
5
default address pointer to DDRAM[1]
6
Icon_ctl
7
Screen_conf
Disp_conf
8
Temp_ctl
9
VLCD_set
10 I2C-bus interface reset
11 HV_gen
Control bit and
register state
-
bit I_D = 1
bit S = 0
bit D = 0
bit C = 0
bit B = 0
bit DL = 1
bit M = 0
bit SL = 0
bit H = 0
-
bit IM = 0
bit IB = 0
bit L = 0
bit P = 0;
bit Q = 0
bit TC1 = 0;
bit TC2 = 0
register VA = 0;
register VB = 0
-
bit S1 = 1;
bit S0 = 0
Description
-
incremental cursor move direction
no display shift
display off
cursor off
cursor character blink off
8-bit interface
1-line display
1:18 multiplex drive mode
normal instruction set
-
character mode, full display
icon blink disabled
default configuration
default configurations
default temperature coefficient
VLCD generator off
-
VLCD generator set to 3 internal stages
(4 voltage multipliers)
Reference
Table 16
Table 18
Table 19
Table 12
Table 22
Table 25
Table 23
Table 24
Table 28
Table 32
-
Table 30
[1] The Busy Flag (BF) indicates the busy state (bit BF = 1) until initialization ends. The busy state lasts 2 ms. The chip may also be
initialized by software (see Table 44 and Table 45).
8.3 Power-down mode
The chip can be put into power-down mode by applying a HIGH-level to pin PD. In
power-down mode all static currents are switched off (no internal oscillator, no bias level
generation and all LCD outputs are internally connected to VSS).
During power-down, information in the RAM and the chip state are preserved. Instruction
execution during power-down is possible when pin OSC is externally clocked.
PCF2119X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 14 April 2011
© NXP B.V. 2011. All rights reserved.
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