PC85133-1(2009) Просмотр технического описания (PDF) - NXP Semiconductors.
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PC85133-1 Datasheet PDF : 41 Pages
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NXP Semiconductors
PCF85133
Universal LCD driver for low multiplex rates
7.16.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 11).
SDA
SCL
Fig 11. Bit transfer
data line
stable;
data valid
change
of data
allowed
mba607
7.16.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START
condition (S).
A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P).
The START and STOP conditions are shown in Figure 12.
SDA
SDA
SCL
S
START condition
Fig 12. Definition of START and STOP conditions
P
STOP condition
SCL
mbc 622
7.16.2 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 13.
PCF85133_1
Product data sheet
MASTER
TRANSMITTER /
RECEIVER
SDA
SCL
SLAVE
RECEIVER
Fig 13. System configuration
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
mga807
Rev. 1 — 17 February 2009
© NXP B.V. 2009. All rights reserved.
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