PC85133-1(2009) Просмотр технического описания (PDF) - NXP Semiconductors.

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PC85133-1
(Rev.:2009)

Universal LCD driver for low multiplex rates

NXP Semiconductors. 

NXP Semiconductors

PCF85133

Universal LCD driver for low multiplex rates

7.12 Subaddress counter

The storage of display data is conditioned by the content of the subaddress counter.

Storage is allowed only when the content of the subaddress counter match with the

hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined

by the device-select command (see Table 12). If the content of the subaddress counter

and the hardware subaddress do not match then data storage is inhibited but the data

pointer is incremented as if data storage had taken place. The subaddress counter is also

incremented when the data pointer overflows.

The storage arrangements described lead to extremely efficient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCF85133 occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character (such as during the 27th

display data byte transmitted in 1:3 multiplex mode).

The hardware subaddress must not be changed whilst the device is being accessed on

the I2C-bus interface.

7.13 Output bank selector

The output bank selector selects one of the four rows per display RAM address for

transfer to the display register. The actual row selected depends on the particular LCD

drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, row 2 and then row 3

• In 1:3 multiplex mode, rows 0, 1 and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

The PCF85133 includes a RAM bank switching feature in the static and 1:2 multiplex drive

modes. In the static drive mode, the bank-select command may request the contents of

row 2 to be selected for display instead of the contents of row 0. In the 1:2 mode, the

contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

7.14 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode

or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The

input bank selector functions independently to the output bank selector.

7.15 Blinker

The display blinking capabilities of the PCF85133 are very versatile. The whole display

can blink at frequencies selected by the blink-select command (see Table 14). The blink

frequencies are fractions of the clock frequency. The ratios between the clock and blink

frequencies depend on the blink mode in which the device is operating (see Table 7).

PCF85133_1

Product data sheet

Rev. 1 — 17 February 2009

© NXP B.V. 2009. All rights reserved.

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