PCF2113AU Просмотр технического описания (PDF) - Philips Electronics

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PCF2113AU

LCD controllers/drivers

Philips Electronics 

Philips Semiconductors

LCD controllers/drivers

Product specification

PCF2113x

A master receiver must signal an end of data to the

transmitter by not generating an acknowledge bit on the

last byte that has been clocked out of the slave. In this

event the transmitter must leave the data line HIGH to

enable the master to generate a STOP condition.

10.2.1 I2C-BUS PROTOCOL

Before any data is transmitted on the I2C-bus, the device

which should respond is addressed first. The addressing is

always carried out with the first byte transmitted after the

START procedure. The I2C-bus configuration for the

different PCF2113x read and write cycles is shown in

Figs 24 to 26. The slow down feature of the I2C-bus

protocol (receiver holds SCL LOW during internal

operations) is not used in the PCF2113x.

10.2.2 DEFINITIONS

• Transmitter: the device which sends the data to the bus

• Receiver: the device which receives the data from the

bus

• Master: the device which initiates a transfer generates

clock signals and terminates a transfer

• Slave: the device addressed by a master

• Multi-master: more than one master can attempt to

control the bus at the same time without corrupting the

message

• Arbitration: procedure to ensure that if more than one

master simultaneously tries to control the bus, only one

is allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clock

signals of two or more devices.

MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

MGA807

Fig.20 System configuration.

handbook, full pagewidth

SDA

SCL

2001 Dec 19

data line

stable;

data valid

change

of data

allowed

Fig.21 Bit transfer.

34

MBC621

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