PCA9559(2003) Просмотр технического описания (PDF) - Philips Electronics
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PCA9559 Datasheet PDF : 11 Pages
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Philips Semiconductors
5-bit multiplexed/1-bit latched 6-bit
I2C EEPROM DIP switch
Product data
PCA9559
AC CHARACTERISTICS
SYMBOL
PARAMETER
MIN.
LIMITS
TYP.
MAX.
UNIT
MUX_IN ⇒ MUX_OUT
tPLH
LOW-to-HIGH transition time
tPHL
HIGH-to-LOW transition time
Select ⇒ MUX_OUT
—
28
37
ns
—
16
21
ns
tPLH
LOW-to-HIGH transition time
tPHL
HIGH-to-LOW transition time
OVERRIDE_N ⇒ NON-MUXED_OUT
—
30
39
ns
—
17
22
ns
tPLH
LOW-to-HIGH transition time
tPHL
HIGH-to-LOW transition time
OVERRIDE_N ⇒ MUX_OUT
—
34
43
ns
—
19
25
ns
tPLH
tPHL
tR
tF
PF
CL
I2C-bus
LOW-to-HIGH transition time
HIGH-to-LOW transition time
Output rise time
Output fall time
Pull-up resistor for outputs
Test load capacitance on outputs
—
31
—
21
1.0
—
1.0
—
1.0
—
—
—
41
ns
27
ns
3
ns/V
3
ns/V
—
ns/V
—
pF
tSCL
SCL clock frequency
10
—
400
kHz
tBUF
Bus free time between a STOP and a START condition
1.3
—
—
µs
tHD:STA
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
600
—
—
ns
tLOW
LOW period of SCL clock
1.3
—
—
µs
tHIGH
HIGH period of SCL clock
600
—
-12
ns
tSU:STA
Set-up time for a repeated START condition
600
—
-32
ns
tHD:DAT
Data hold time
0
—
10
ns
tSU:DAT
Data set-up time
100
—
-100
ns
tSP
Data spike time
0
—
50
ns
tSU:STO
Set-up time for STOP condition
600
—
10
ns
tR
Rise time for both SDA and SCL signals (10 - 400 pF bus)
20
—
300
ns
tI
Fall time for both SDA and SCL signals (10 - 400 pF bus)
20
—
300
ns
CL
Capacitive load for each bus line
—
—
400
pF
TW
Write cycle time1
—
15
—
ms
NOTE:
1. WRITE CYCLE time can only be measured indirectly during the write cycle. During this time, the device will not acknowledge its I2C Address.
2003 Jun 27
7
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