PCA9559(2003) Просмотр технического описания (PDF) - Philips Electronics

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PCA9559
(Rev.:2003)

5-bit multiplexed/1-bit latched 6-bit I2C EEPROM DIP switch

Philips Electronics 

Philips Semiconductors

5-bit multiplexed/1-bit latched 6-bit

I2C EEPROM DIP switch

Product data

PCA9559

FUNCTIONAL DESCRIPTION

When the MUX_SELECT signal is logic 0, the multiplexer will select

the data from the non-volatile register to drive on the MUX_OUT

pins. When the MUX_SELECT signal is logic 1, the multiplexer will

select the MUX_IN lines to drive on the MUX_OUT pins. The

MUX_SELECT signal is also used to latch the NON_MUXED_OUT

signal which outputs data from the non-volatile register. The

NON_MUXED_OUT signal latch is transparent when MUX_SELECT

is in a logic 0 state, and will latch data when MUX_SELECT is in a

logic 1 state. When the active-LOW OVERRIDE_N signal is set to

logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will

be driven to logic 0. This information is summarized in Table 1.

The Write Protect (WP) input is used to control the ability to write the

contents of the 6-bit non-volatile register. If the WP signal is logic 0,

the I2C-bus will be able to write the contents of the non-volatile

register. If the WP signal is logic 1, data will not be allowed to be

written into the non-volatile register.

The factory default for the contents of the non-volatile register are all

logic 0. These stored values can be read or written using the

I2C-bus (described in the next section).

The OVERRIDE_N, WP, MUX_IN, and MUX_SELECT signals have

internal pull-up resistors. See the DC and AC Characteristics for

hysteresis and signal spike suppression figures.

FUNCTION TABLE

OVERRIDE_N

MUX_SELECT

MUX_OUT

OUTPUTS

NON_MUXED_OUT

OUTPUT

0

0

All 0’s

All 0’s

0

1

MUX_IN

Latched

inputs NON_MUXED_OUT 1

1

0

From non-

volatile

register

From non-volatile

register

1

1

MUX_IN

inputs

From non-volatile

register

NOTE:

1. NON_MUXED_OUT state will be the value present on the output

at the time of the MUX_SELECT input transitioned from a logic 0

to a logic 1 state.

I2C INTERFACE

Communicating with this device is initiated by sending a valid

address on the I2C-bus. The address format (see FIgure 1) has 5

fixed bits and two user-programmable bits followed by a 1-bit

read/write value which determines the direction of the data transfer.

MSB

LSB

1 0 0 1 1 A1 A0 R/W

FIXED

HARDWARE

SELECTABLE

Figure 2. I2C Address Byte

Following the address and acknowledge bit are 8 data bits which,

depending on the read/write bit in the address, will read data from or

write data to the non-volatile register. Data will be written to the

register if the read/write bit is logic 0 and the WP input is logic 0.

Data will be read from the register if the bit is logic 1. The four

high-order bits are latched outputs, while the four low order bits are

multiplexed outputs (Figure 3).

NOTE:

1. To ensure data integrity, the non-volatile register must be

internally write protected when VCC to the I2C-bus is powered

down or VCC to the component is dropped below normal

operating levels.

MSB

0

LSB

0

NON-

MUXED

DATA

MUX

DATA E

MUX MUX

DATA D DATA C

MUX

DATA B

MUX

DATA A

Figure 3. I2C Data Byte

POWER-ON RESET (POR)

When power is applied to VCC, an internal power-on reset holds the

PCA9559 in a reset state until VCC has reached VPOR. At that point,

the reset condition is released and the PCA9559 volatile registers

and I2C/SMBus state machine will initialize to their default states.

The MUX_OUT and NON_MUXED_OUT pin values depend on:

- the OVERRIDE # and MUX_SELECT logic levels

- the previously stored values in the EEPROM register/current

MUX_IN pin values as shown in the Function Table.

2003 Jun 27

3

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