PCA9546ABS Просмотр технического описания (PDF) - NXP Semiconductors.
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PCA9546ABS Datasheet PDF : 25 Pages
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NXP Semiconductors
PCA9546A
4-channel I2C-bus switch with reset
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9546A, which will be stored in the control register. If multiple bytes are
received by the PCA9546A, it will save the last byte received. This register can be written
and read via the I2C-bus.
channel selection bits
(read/write)
76543210
X X X X B3 B2 B1 B0
channel 0
channel 1
channel 2
channel 3
002aab190
Fig 6. Control register
6.2.1 Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This register is written after the PCA9546A has been addressed. The
4 LSBs of the control byte are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a STOP condition has been
placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when
the channel is made active, so that no false conditions are generated at the time of
connection.
Table 4. Control register: Write—channel selection; Read—channel status
D7 D6 D5 D4 B3 B2 B1 B0 Command
0
channel 0 disabled
X
X
X
X
X
X
X
1
channel 0 enabled
0
channel 1 disabled
X
X
X
X
X
X
X
1
channel 1 enabled
0
channel 2 disabled
X
X
X
X
X
X
X
1
channel 2 enabled
0
channel 3 disabled
X
X
X
X
X
X
X
1
channel 3 enabled
0
0
0
0
0
0
0
0
no channel selected;
power-up/reset default state
Remark: Several channels can be enabled at the same time. Example: B3 = 0, B2 = 1,
B1 = 1, B0 = 0, means that channel 0 and channel 3 are disabled and channel 1 and
channel 2 are enabled. Care should be taken not to exceed the maximum bus
capacitance.
PCA9546A_5
Product data sheet
Rev. 05 — 2 July 2009
© NXP B.V. 2009. All rights reserved.
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