PCA9539 Просмотр технического описания (PDF) - NXP Semiconductors.
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PCA9539 Datasheet PDF : 31 Pages
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NXP Semiconductors
PCA9539; PCA9539R
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
data from
shift register
data from
shift register
write
configuration
pulse
configuration
register
DQ
FF
CK Q
write pulse
read pulse
data from
shift register
write polarity
pulse
DQ
FF
CK
output port
register
Q1
Q2
input port
register
DQ
FF
CK
polarity inversion
register
DQ
FF
CK
At power-on reset, all registers return to default values.
Fig 6. Simplified schematic of I/Os
output port
register data
VDD
I/O pin
VSS
input port
register data
to INT
polarity
inversion
register data
002aad723
6.6 Bus transactions
6.6.1 Writing to the port registers
Data is transmitted to the PCA9539; PCA9539R by sending the device address and
setting the least significant bit to a logic 0 (see Figure 5 “PCA9539; PCA9539R device
address”). The command byte is sent after the address and determines which register will
receive the data following the command byte.
The eight registers within the PCA9539; PCA9539R are configured to operate as four
register pairs. The four pairs are Input ports, Output ports, Polarity inversion ports, and
Configuration ports. After sending data to one register, the next data byte will be sent to
the other register in the pair (see Figure 7 and Figure 8). For example, if the first byte is
sent to Output port 1 (register 3), then the next byte will be stored in Output port 0
(register 2). There is no limitation on the number of data bytes sent in one write
transmission. In this way, each 8-bit register may be updated independently of the other
registers.
PCA9539_PCA9539R_5
Product data sheet
Rev. 05 — 28 July 2008
© NXP B.V. 2008. All rights reserved.
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