PCA9518 Просмотр технического описания (PDF) - NXP Semiconductors.

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PCA9518

Expandable 5-channel I2C-bus hub

NXP Semiconductors. 

NXP Semiconductors

PCA9518

Expandable 5-channel I2C-bus hub

Standard-mode devices and multiple masters are possible. Please see application note

AN255, I2C/SMBus Repeaters, Hubs and Expanders for additional information on sizing

resistors.

7. Application design-in information

A typical application is shown in Figure 5. In this example, the system master is running

on a 3.3 V I2C-bus while the slaves are connected to a 3.3 V or 5 V bus. All buses run at

100 kHz unless slave 3, slave 4 and slave 5 are isolated from the bus. Then the master

bus and slave 1, slave 2 and slave 6 can run at 400 kHz.

Any segment of the hub can talk to any other segment of the hub. Bus masters and slaves

can be located on any segment with 400 pF load allowed on each segment.

The PCA9518 is 5 V tolerant, so it does not require any additional circuitry to translate

between the different bus voltages.

When one port of the PCA9518 is pulled LOW by a device on the I2C-bus, a CMOS

hysteresis type input detects the falling edge and drives the EXPxxx1 line LOW, when the

EXPxxx1 voltage is less than 0.5VCC, the other ports are pulled down to the VOL of the

PCA9518 which is typically 0.5 V.

In order to illustrate what would be seen in a typical application, refer to Figure 6. If the

bus master in Figure 5 were to write to the slave through the PCA9518, we would see the

waveform shown in Figure 6. This looks like a normal I2C-bus transmission except for the

small foot preceding each clock LOW-to-HIGH transition and proceeding each data

LOW-to-HIGH transition for the master. The foot height is the difference between the LOW

level driven by the master and the higher voltage LOW level driven by the PCA9518

repeater. Its width corresponds to an effective clock stretching coming from the PCA9518

that delays the rising edge of the clock. That same magnitude of delay is seen on the

rising edge of the data. The foot on the rising edge of the data is extended through the 9th

clock pulse as the PCA9518 repeats the acknowledge from the slave to the master. The

clock of the slave looks normal except the VOL is the ~0.5 V level generated by the

PCA9518. The SDA at the slave has a particularly interesting shape during the 9th clock

cycle where the slave pulls the line below the value driven by the PCA9518 during the

acknowledge and then returns to the PCA9518 level creating a foot before it completes

the LOW-to-HIGH transition. SDA lines other than the one with the master and the one

with the slave have a uniform LOW level driven by the PCA9518 repeater.

The other four waveforms are the expansion bus signals and are included primarily for

timing reference points. All timing on the expansion bus is with respect to 0.5VCC.

EXPSDA1 is the expansion bus that is driven LOW whenever any SDA pin falls below

0.3VCC. EXPSDA2 is the expansion bus that is driven LOW whenever any pin is ≤0.4 V.

EXPSCL1 is the expansion bus that is driven LOW whenever any SCL pin falls below

0.3VCC. EXPSCL2 is the expansion bus that is driven LOW whenever any SCL pin is

≤0.4 V. The EXPSDA2 returns HIGH after the SDA pin that was the last one being held

below 0.4 V by an external driver starts to rise. The last SDA to rise above 0.4 V is held

down by the PCA9518 to ~0.5 V until after the delay of the circuit which determines that it

was the last to rise, then it is allowed to rise above the ~0.5 V level driven by the

PCA9518. Considering the bus 0 SDA to be the last one to go above 0.4 V, then the

EXPSDA1 returns to HIGH after the EXPSDA2 is HIGH and either the bus 0 SDA rise time

PCA9518_5

Product data sheet

Rev. 05 — 2 December 2008

© NXP B.V. 2008. All rights reserved.

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