PC85132/232-1 Просмотр технического описания (PDF) - NXP Semiconductors.
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PC85132/232-1 Datasheet PDF : 65 Pages
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NXP Semiconductors
PCA85132
LCD driver for low multiplex rates
Table 10. Bank-select - command bit description …continued
See Section 7.5.4 on page 25.
Bit
Symbol Value
Description
Static
1:2 multiplex[1]
0
O
output bank selection; retrieval of LCD display data
0[2]
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
[2] Default value.
7.1.5 Command: blink-select
The blink-select command allows configuring the blink mode and the blink frequency.
Table 11. Blink-select - command bit description
See Section 7.1.6.6 on page 10.
Bit
Symbol Value
Description
7 to 3 -
1111 0
fixed value
2
AB
blink mode selection
0[1]
normal blinking[2]
1
alternate RAM bank blinking[3]
1 to 0 BF[1:0]
blink frequency selection
00[1]
off
01
1
10
2
11
3
[1] Default value.
[2] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.1.6 Clock frequency and timing
The timing of the PCA85132 organizes the internal data flow of the device. The timing
includes the transfer of display data from the display RAM to the display segment outputs
and therefore the frame frequency.
7.1.6.1 Clock source selection
The PCA85132 can be configured to use either the built-in oscillator or an external clock
as clock source:
Internal clock — To enable the internal oscillator, pin OSC has to be connected to VSS.
Pin CLK then becomes an output. For further information on the internal clock, see
Section 7.1.6.2.
External clock — To enable the use of an external clock, pin OSC has to be connected to
VDD. Pin CLK then becomes an input for the external clock frequency fclk(ext). For further
information on the external clock, see Section 7.1.6.3.
Figure 3 illustrates the frequency generation of the PCA85132.
PCA85132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 9 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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