PC8260 Просмотр технического описания (PDF) - Atmel Corporation

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PC8260

PowerPC-based Communications Processors

Atmel Corporation 

PC8260 PowerQUICC II

System Interface Unit

(SIU)

The SIU consists of the following:

• A 60x-compatible parallel system bus configurable to 64-bit data width. The PC8260

supports 64-, 32-, 16-, and 8-bit port sizes.The PC8260 internal arbiter arbitrates

between internal components that can access the bus (system core, PCI bridge,

CPM, and one external master). This arbiter can be disabled, and an external

arbiter can be used if necessary.

• A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is

used to enhance the operation of the very high-speed communication controllers.

Without requiring extensive manipulation by the core, the bus can be used to store

connection tables for ATM or buffer descriptors (BDs) for the communication

channels or raw data that is transmitted between channels. The local bus is

synchronous to the 60x bus and runs at the same frequency.

• The local bus can be configured as a 32-bit data and up to 66 MHz PCI (version 2.1)

bus. In PCI mode the bus can be programmed as a host or as an agent. The PCI

bus can be configured to run synchronously or asynchronously to the 60x bus. The

PC8260 has an internal PCI bridge with an efficient 60x-to-PCI DMA for memory

block transfers.

• Applications that require both the local bus and PCI bus need to connect an external

PCI bridge.

• A memory controller supporting 12 memory banks that can be allocated for either

the system or the local bus. The memory controller is an enhanced version of the

PC8260 memory controller. It supports three user-programmable machines.

Besides supporting all PC8260 features, the memory controller also supports

SDRAM with page mode and address data pipeline

• Supports JTAG controller IEEE 1149.1 test access port (TAP).

• A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt

timer, and other system functions useful in embedded applications.

• Glueless interface to L2 cache and 4-/16-K-entry CAM.

5

2131B–HIREL–02/03

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