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PC8260VTPU200

PowerPC-based Communications Processors

Atmel Corporation 

PC8260 PowerQUICC II

PC8260 Architecture

General Overview

The PC8260 has two external buses to accommodate bandwidth requirements from the

highspeed system core and the very fast communications channels. The device is com-

posed of the following three major functional blocks:

• A 64-bit PowerPC core derived from the EC603e with MMUs and caches.

• A system interface unit (SIU).

• A communications processor module (CPM). Both the system core and the CPM

have an internal PLL, which allows independent optimization of the frequencies at

which they run. The system core and CPM are both connected to the 60x bus.

Figure 1. PC8260 Block Diagram

EC603e

PowerPC

Core

16-Kbyte

Instruction Cache

IMMU

16-Kbyte

Data Cache

DMMU

60x Bus

60x-to-PCI Bus Bridge

(PC8265 only)

60x-to-Local Bus Bridge

Memory Controller

PCI/

Local

Bus

Timers

Parallel I/O

Baud Rate

Generator

Interrupt

Controller

24-Kbyte Dual-

Port RAM

Serial DMAs

32-Bit RISC Communications

Processor (CP) and

Program ROM

4 Virtual

IDMAs

Bus Interface Unit

Clock Counter

System Functions

MCC MCC FCC FCC FCC SCC SCC SCC SCC SMC SMC SPI I 2C

Time Slot Assigner

8 TDMs

Serial Interface

2 UTOPIA

3 Mlls Non-Multiplexed I/O

3

2131B–HIREL–02/03

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