PC8245MTPU300D Просмотр технического описания (PDF) - Atmel Corporation

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производитель

PC8245MTPU300D

Integrated Processor Family

Atmel Corporation 

Recommended

Operating Conditions

Following table provides the recommended operating conditions for the PC8245.

Recommended Operating Conditions

Symbol

Characteristic(1)(6)

Recommended Value

Unit

Notes

VDD

OVDD

GVDD

AVDD

AVDD2

LVDD

Supply Voltage

I/O Buffer supply for PCI and Standard

Supply Voltages for Memory Bus Drivers

CPU PLL Supply Voltage

PLL Supply Voltage – Peripheral Logic

PCI Reference

2.0 ± 100 mV

3.3 ± 0.3

3.3 ± 5 %

2.0 ± 100 mV

2.0 ± 100 mV

5.0 ± 5 %

3.3 ± 0.3

V

(5)

V

(5)

V

(7)

V

(5)

V

(5)

V

(2)(8)(9)

V

(3)(8)(9)

VIN

Input Voltage

PCI Inputs

All Other Inputs

0 to 3.6 or 5.75

0 to 3.6

V

(2)(3)

V

(4)

Tc

Notes:

Tcase

-55 to 125

°C

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not

guaranteed.

2. PCI pins are designed to withstand LVDD + 0.5V DC when LVDD is connected to a 5.0V DC power supply.

3. PCI pins are designed to withstand LVDD + 0.5V DC when LVDD is connected to a 3.3V DC power supply.

4. Caution: Input voltage (VIN) must not be greater than the supply voltage (VDD/AVDD/AVDD2) by more than 2.5V at all times

including during power-on reset. Input voltage (VIN) must not be greater than GVDD/OVDD by more than 0.6V at all times

including during power-on reset.

5. Caution: OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8V at any time including during power-on reset. This limit

may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

6. Caution: VDD/AVDD/AVDD2 must not exceed OVDD by more than 0.6V at any time including during power-on reset. This limit

may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

7. Caution: GVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8V at any time including during power-on reset. This limit

may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

8. Caution: LVDD must not exceed VDD/AVDD/AVDD2 by more than 5.4V at any time including during power-on reset. This limit

may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

9. Caution: LVDD must not exceed OVDD by more than 3.0V at any time including during power-on reset. This limit may be

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

12 PC8245

2171D–HIREL–06/04

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