PC8245MTPU333D Просмотр технического описания (PDF) - Atmel Corporation

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PC8245MTPU333D

Integrated Processor Family

Atmel Corporation 

3. This pin has an internal pull-up resistor which is enabled only when the PC8245 is in the reset state. The value of the inter-

nal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during reset.

4. This pin is a reset configuration pin.

5. DL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the PC8245 is in the reset

state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into config-

uration bits during reset.

6. Multi-pin signals such as AD[31:0] or MDL[0:31] have their physical package pin numbers listed in order, corresponding to

the signal names. Example: AD0 is on pin C22, AD1 is on pin D22, ..., AD31 is on pin V25.

7. GNT4 is a reset configuration pin and has an internal pull-up resistor which is enabled only when the PC8245 is in the reset

state.

8. Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this PCI control pin to LVDD.

9. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 4 on page 23.

10. Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this pin to OVDD.

11. Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this pin to GVDD.

12. This pin has an internal pull-up resistor which is enabled at all times. The value of the internal pull-up resistor is not guaran-

teed, but is sufficient to prevent unused inputs from floating.

13. External PCI clocking source or fan-out buffer may be required for system if using the PC8245 DUART functionality since

PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART mode.

14. This pin is a multiplexed signal and appears more than once in this table.

15. This pin is affected by programmable PCI_HOLD_DEL parameter.

16. This pin is an open drain signal.

17. This pin can be programmed to be driven (default) or can be programmed (in PMCR2) to be open drain.

18. This pin is a sustained three-state pin as defined by the PCI Local Bus Specification.

19. OSC_IN utilizes the 3.3V PCI interface driver which is 5V tolerant, see Table “Recommended Operating Conditions” on page

12 for details.

20. PLL_CFG[0:4] signals are sampled a few clocks after the negation of HRST_CPU and HRST_CTRL.

21. SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev 1.1 (A). These signals use

DRV_MEM_CLK for chip Rev 1.2 (B).

22. The 266 and 300 MHz part offerings can be ran at a source voltage of 1.8 ± 100 mV or 2.0 ± 100 mV. Note that source volt-

age should be 2.0 ± 100 mV for 333- and 350-MHz parts.

23. This pin was formally LAVDD on the PC8240. It is a no connect on the PC8245. This should not pose a problem when

replacing an PC8240 with an PC8245.

24. The driver capability of this pin is hardwired to 40Ω and cannot be changed.

10 PC8245

2171D–HIREL–06/04

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