ML6401 Просмотр технического описания (PDF) - Micro Linear Corporation
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ML6401 Datasheet PDF : 10 Pages
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ML6401
PIN CONFIGURATION
ML6401-1
24-Pin SOIC (S24W)
OE
GNDO
D0
D1
D2
D3
D4
D5
D6
D7
VDDO
CLK
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
TOP VIEW
GNDD
VIN–
VIN–BIAS
GNDA
GNDA
VIN+
VDDA
VREFIN
VREFOUT
VDDA
VDDA
VDDD
ML6401-3
16-Pin SOIC (S16N)
D0
1
D1
2
D2
3
D3
4
D4
5
D5
6
D6
7
D7
8
16
OE
15
GNDD
14
GNDA
13
VIN+
12
VDDA
11
VDDD
10
CLK
9
VDDD
TOP VIEW
PIN DESCRIPTION (Pin numbers in parentheses are for S16N package)
PIN
1 (16)
2
3 (1)
4 (2)
5 (3)
6 (4)
7 (5)
8 (6)
9 (7)
10 (8)
11
12 (10)
NAME
OE
DESCRIPTION
Output Enable. A logic low signal
on this pin enables the outputs.
GNDO
D0
Output ground pin.
D0 (LSB) output signal (TTL
compatible).
D1
D1 output signal (TTL compatible).
D2
D2 output signal (TTL compatible).
D3
D3 output signal (TTL compatible).
D4
D4 output signal (TTL compatible).
D5
D5 output signal (TTL compatible).
D6
D6 output signal (TTL compatible).
D7
D7 (MSB) output signal (TTL
compatible).
VDDO Output supply pin.
CLK Clock input pin.
PIN NAME
13 (9,11) VDDD
DESCRIPTION
Digital supply pin.
14 (12) VDDA Analog supply pin.
15 (12) VDDA Analog supply pin.
16
VREFOUT Full scale reference output.
Connect to pin 17 for self bias.
(VRTS on 1175) (ML401-1 only)
17
VREFIN Full scale reference input.
Connect to pin 16 for self bias.
(VRT on 1175) (ML401-1 only)
18 (12)
19 (13)
20 (14)
21 (14)
22
VDDA
VIN+
GNDA
GNDA
VIN–BIAS
Analog supply pin.
Input signal.
Analog ground.
Analog ground.
Common mode bias output.
Connect to pin 23 for self bias.
(VRBS on 1175) (ML401-1 only)
23
VIN–
Common mode bias input.
Connect to pin 22 for self bias.
Drive with the negative input if
differential input is being used.
(VRB on 1175)
(ML401-1 only)
24 (15) GNDD Digital Ground.
2
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