MAX456 Просмотр технического описания (PDF) - Maxim Integrated
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MAX456 Datasheet PDF : 12 Pages
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8 x 8 Video Crosspoint Switch
________________Typical Application
Figure 2 shows a typical application of the MAX456 with
MAX470 quad, gain-of-two buffers at the outputs to
drive 75Ω loads. This application shows the MAX456
digital-switch control interface set up in the 7-bit paral-
lel mode. The MAX456 uses 7 data lines and 2 control
lines (WR and LATCH). Two additional lines may be
needed to control CE and LOAD when using multiple
MAX456s.
The input/output information is presented to the chip at
A2-A0 and D3-D0 by a parallel printer port. The data is
stored in the 1st-rank registers on the rising edge of
WR. When the LATCH line goes high, the switch con-
figuration is loaded into the 2nd-rank registers, and all 8
outputs enter the new configuration at the same time.
Each 7-bit word updates only one output buffer at a
time. If several buffers are to be updated, the data is
individually loaded into the 1st-rank registers. Then, a
single LATCH pulse is used to reconfigure all channels
simultaneously.
The short Basic program in Figure 3 loads programming
data into the MAX456 from any IBM PC or compatible.
It uses the computer’s “LPT1” output to interface to the
circuit, then automatically finds the address for LPT1
and displays a table of valid input values to be used.
The program does not keep track of previous com-
mands, but it does display the last data sent to LPT1,
which is written and latched with each transmission.
8-INPUT
VIDEO
CHANNELS
DB-25
14
1
2
3
4
5
18
19
6
20
21
7
8
22
23
24
25
MAX470
5 IN0
OUT0 39
1 IN0
OUT0 16
75Ω
AV = 2
7 IN1
9 IN2
OUT1 37
OUT2 35
3 IN1
6 IN2
OUT1 14
OUT2 11
75Ω
11 IN3
OUT3 33
8 IN3
OUT3 9
13 IN4
OUT4 31
15 IN5
17 IN6
19 IN7
MAX456 OUT5 29
OUT6 27
OUT7 25
V+ GND V-
10
2,7,15 4,5,12,13
CE 24
-5V
EDGE/LEVEL 14
22 LATCH
LOAD 8
21 WR
V+ 40
V+ 26
+5V
2 D0/SER IN
1 D1/SER OUT
38 D2
36 D3
6 A0
4 A1
3 A2
AGND 28, 30, 32
DGND 10, 12
V- 20
V- 34
CE 23
SER/PAR 18
V+ 16
+5V
-5V
ALL BYPASS CAPACITORS 0.1µF CERAMIC
Figure 2. Typical Application Circuit
8 _______________________________________________________________________________________
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