P89C51RB2 Просмотр технического описания (PDF) - Philips Electronics

Номер в каталоге

Компоненты Описание

производитель

P89C51RB2

80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

Philips Electronics 

Philips Semiconductors

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

Product data

P89C51RB2/P89C51RC2/

P89C51RD2Hxx

DESCRIPTION

The P89C51RB2/RC2/RD2Hxx device contains a non-volatile

16KB/32KB/64KB Flash program memory that is both parallel

programmable and serial In-System and In-Application

Programmable. In-System Programming (ISP) allows the user to

download new code while the microcontroller sits in the application.

In-Application Programming (IAP) means that the microcontroller

fetches new program code and reprograms itself while in the

system. This allows for remote programming over a modem link.

A default serial loader (boot loader) program in ROM allows serial

In-System programming of the Flash memory via the UART without

the need for a loader in the Flash code. For In-Application

Programming, the user program erases and reprograms the Flash

memory by use of standard routines contained in ROM.

This device executes one machine cycle in 6 clock cycles, hence

providing twice the speed of a conventional 80C51. An OTP

configuration bit lets the user select conventional 12 clock timing

if desired.

This device is a Single-Chip 8-Bit Microcontroller manufactured in

advanced CMOS process and is a derivative of the 80C51

microcontroller family. The instruction set is 100% compatible with

the 80C51 instruction set.

The device also has four 8-bit I/O ports, three 16-bit timer/event

counters, a multi-source, four-priority-level, nested interrupt structure,

an enhanced UART and on-chip oscillator and timing circuits.

The added features of the P89C51RB2/RC2/RD2Hxx makes it a

powerful microcontroller for applications that require pulse width

modulation, high-speed I/O and up/down counting capabilities such

as motor control.

FEATURES

• 80C51 Central Processing Unit

• On-chip Flash Program Memory with In-System Programming

(ISP) and In-Application Programming (IAP) capability

• Boot ROM contains low level Flash programming routines for

downloading via the UART

• Can be programmed by the end-user application (IAP)

• Parallel programming with 87C51 compatible hardware interface

to programmer

• Six clocks per machine cycle operation (standard)

• 12 clocks per machine cycle operation (optional)

• Speed up to 20 MHz with 6 clock cycles per machine cycle

(40 MHz equivalent performance); up to 33 MHz with 12 clocks

per machine cycle

• Fully static operation

• RAM expandable externally to 64 kbytes

• Four interrupt priority levels

• Seven interrupt sources

• Four 8-bit I/O ports

• Full-duplex enhanced UART

– Framing error detection

– Automatic address recognition

• Power control modes

– Clock can be stopped and resumed

– Idle mode

– Power down mode

• Programmable clock out

• Second DPTR register

• Asynchronous port reset

• Low EMI (inhibit ALE)

• Programmable Counter Array (PCA)

– PWM

– Capture/compare

2002 May 24

1

853-2349 28312

Share Link: