MH1S72CPG-10 Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC
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MH1S72CPG-10 Datasheet PDF : 47 Pages
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
Serial Presence Detect Table
Byte
Function described
0
Defines # bytes written into serial memory at module mfgr
1
Total # bytes of SPD memory device
2
Fundamental memory type
3
# Row Addresses on this assembly
4
# Column Addresses on this assembly
5
# Module Banks on this assembly
6
Data Width of this assembly...
7
... Data Width continuation
8
Voltage interface standard of this assembly
9
SDRAM Cycletime at Max. Supported CAS Latency (CL). -10
Cycle time for CL=3
-12
-15
10
SDRAM Access from Clock
-10
tAC for CL=3
-12
-15
11
DIMM Configuration type (Non-parity,Parity,ECC)
12
Refresh Rate/Type
13
SDRAM width,Primary DRAM
14
Error Checking SDRAM data width
15 Minimum Clock Delay,Back to Back Random Column Addresses
16
Burst Lengths Supported
17
# Banks on Each SDRAM device
18
CAS# Latency
19
CS# Latency
20
Write Latency
21
SDRAM Module Attributes
22
SDRAM Device Attributes:General
23
SDRAM Cycle time(2nd highest CAS latency)
-10
Cycle time for CL=2
-12
-15
24
SDRAM Access form Clock(2nd highest CAS latency) -10
tAC for CL=2
-12
-15
25
SDRAM Cycle time(3rd highest CAS latency)
-10
Cycle time for CL=1
-12
-15
26
SDRAM Access form Clock(3rd highest CAS latency) -10
tAC for CL=1
-12
-15
27
Precharge to Active Minimum
-10
-12
-15
28
Row Active to Row Active Min.
-10
-12
-15
SPD enrty data
128
256 Bytes
SDRAM
A0-A10
A0-A7
1BANK
x72
0
LVTTL
10ns
12ns
15ns
8ns
8ns
9ns
ECC
self refresh(15.625uS)
x16
x8
1
1/2/4/8
2bank
CL=1/2/3
0
0
non-buffered,non-registered
Precharge All,Auto precharge
15ns
15ns
20ns
9ns
9.5ns
12ns
30ns
30ns
30ns
27ns
27ns
30ns
30ns
30ns
40ns
20ns
24ns
30ns
SPD DATA(hex)
80
08
04
0B
08
01
48
00
01
A0
C0
F0
80
80
90
02
80
10
08
01
0F
02
06
01
01
00
06
F0
F0
FF
90
95
C0
78
78
78
6C
6C
78
1E
1E
28
14
18
1E
MIT-DS-0089-3.0
MITSUBISHI
ELECTRIC
( 4 / 47 )
28.Mar.1997
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