P1818D Просмотр технического описания (PDF) - Alliance Semiconductor
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P1818D Datasheet PDF : 8 Pages
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P1818/19/20/21/22
®
Frequency vs. Deviation (P1818A and P1818H)
Frequency
10 MHz
15 MHz
20 MHz
Deviation in P1818A
SRS = 1
-4.4%
-1.8%
-0.8%
SRS = 0
-3.3%
-1.26%
-0.6%
Deviation in P1818H
D_C = 1
-4.4%
-1.8%
-0.8%
D_C = 0
±2.2%
±0.9%
±0.4%
Pin Description
Pin
number
Name
Type
Description
1
XIN
I
Connect to externally generated clock signal or crystal.
2
VSS
P
Ground Connection. Connect to system ground.
3
SRS
I
Spread Range Select. Digital logic input used to select frequency devi-
ation (see Spread Deviation Selections). This pin has an internal pull-
up resistor.
31
D_C
4
ModOut
5
REF
5/61
FRS
61
PD#
7
VDD
8
XOUT
81
MRS
I
Digital logic input used to select Down (LOW) or Center (HIGH) Spread
Options (see Spread Deviation Selections). This pin has an internal
pull-up resistor.
O
Spread Spectrum clock output (see Input Frequency and Modulation
Rate Selections and Spread Deviation Selections).
O
Non-modulated reference output clock of the input frequency.
I
Frequency Range Select. Digital logic input used to select input fre-
quency range (see Input Frequency and Modulation Rate Selections).
This pin has an internal pull-up resistor.
I
Power-Down control pin. Pull LOW to enable Power-Down mode. This
pin has an internal pull-up resistor.
P
Connect to +3.3V
I
Connect to crystal. No connect if externally generated clock signal is
used.
I
Modulation Rate Select. Digital logic input used to select Modulation
Rate (see Spread Deviation Selections). This pin has an internal pull-
up resistor.
1. Please refer to Figure 1 for pin assignment.
March 2003
Low Power Mobile VGA EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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