P0111MA5AL3 Просмотр технического описания (PDF) - STMicroelectronics
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P0111MA5AL3 Datasheet PDF : 9 Pages
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Characteristics
P011xx
Figure 5.
Relative variation of gate trigger, Figure 6.
holding and latching current versus
junction temperature
Relative variation of holding
current versus gate-cathode
resistance (typical values)
IGT,IH,IL[Tj] / IGT,IH,IL[Tj=25°C]
6
5
4
3
IGT
2
1
IH & IL
RGK = 1kΩ
Tj(°C)
0
-40
-20
0
20
40
60
typical values
80 100 120 140
IH[RGK] / IH[RGK=1kΩ]
20
18
16
14
12
10
8
6
4
2
0
1E-2
RGK(kΩ)
1E-1
1E+0
Tj = 25°C
1E+1
Figure 7.
Relative variation of dV/dt immunity Figure 8.
versus gate-cathode resistance
(typical values).
Relative variation of dV/dt immunity
versus gate-cathode capacitance
(typical values)
dV/dt[RGK] / dV/dt[RGK=1kΩ]
10.0
Tj = 125°C
VD = 0.67 x VDRM
dV/dt[CGK] / dV/dt[RGK=1kΩ]
10
VD = 0.67 x VDRM
Tj = 125°C
RGK = 1kΩ
8
6
1.0
4
0.1
0
RGK(kΩ)
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
2
CGK(nF)
0
0
1
2
3
4
5
6
7
Figure 9.
Surge peak on-state current versus Figure 10. Non-repetitive surge peak on-state
number of cycles
current and corresponding value
of I²t
ITSM(A)
8
7
6
5
4
3
2
1
0
1
Repetitive
Tamb=25°C
Non repetitive
Tj initial=25°C
Number of cycles
10
100
tp=10ms
One cycle
1000
ITSM(A), I2t (A2s)
100.0
sinusoidal pulse with
10.0
width tp < 10ms
Tj initial = 25°C
ITSM
1.0
0.1
0.01
tp(ms)
0.10
1.00
I2t
10.00
4/9
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