OX16C954 Просмотр технического описания (PDF) - Unspecified
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OX16C954 Datasheet PDF : 54 Pages
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OXFORD SEMICONDUCTOR LTD.
OX16C954 rev B
TQFP PLCC Dir1 Name
Description
Processor Interface Pins in Motorola Mode (I/M# = ‘0’) Contd.
15 to 11 5 to 1 I/O DB[7:0]
Eight-bit 3-state data bus.
9 to 7 68 to 66
31
18
I
R/W#
Read-not-write signal. This signal should be high during read cycles and
low during write cycles.
Serial Port Pins
72
53
69
51
32
19
29
17
O SOUT[3]
O SOUT[2]
O SOUT[1]
O SOUT[0]
Serial data output, Uart 3
Serial data output, Uart 2
Serial data output, Uart 1
Serial data output, Uart 0
72
53
O IrDA_Out[3] UART IrDA data outputs, each Uart, respectively.
69
51
O IrDA_Out[2] Serial data output pins are redefined as IrDA data outputs when MCR[6]
32
19
O IrDA_Out[1] of the corresponding UART channel is set in enhanced mode
29
17
O IrDA_Out[0]
75
56
O RTS[3]#
Active-low Request-To-Send output, for each uart respectively.
66
48
O RTS[2]#
Whenever the automated RTS# flow control is enabled for the
35
22
O RTS[1]#
corresponding channel, the RTS# pin is de-asserted and re-asserted if the
26
14
O RTS[0]#
receiver FIFO reaches or falls below a pair of programmed flow control
thresholds, respectively. The state is controlled by bit 1 of the MCR.
RTS may also be used as a general-purpose output.
77
58
O DTR[3]#
Active-low modem “data-terminal-ready output”, for each uart respectively.
64
46
O DTR[2]#
If automated DTR# flow control is enabled for the corresponding UART
37
24
O DTR[1]#
channel, the DTR# pin is asserted and deasserted if the receiver FIFO
24
12
O DTR[0]#
reaches or falls below the channel’s programmed thresholds, respectively.
The state is set by bit 0 of the MCR. DTR may also be used as a general
purpose output.
77
58
O 485_En[3]
64
46
O 485_En[2] In RS485 half-duplex mode, the DTR# pin of each UART channel may be
37
24
O 485_En[1] programmed to reflect the state of the channel’s transmitter empty bit (or
24
12
O 485_En[0] its inverse) to automatically control the direction of the RS485 transceiver
buffer (see register ACR[4:3])
77
58
O TxClkOut[3]
64
46
O TxClkOut[2] Transmitter 1x (or baud rate generator output) clock. For isochronous
37
24
O TxClkOut[1] applications, the 1x (or Nx) transmitter clock may be asserted on the
24
12
O TxClkOut[0] uart’s DTR# pin (see CKS[5:4]).
4
63
I
SIN[3]
Serial data input, UART 3.
57
41
I
SIN[2]
Serial data input, UART 2.
44
29
I
SIN[1]
Serial data input, UART 1.
17
7
I
SIN[0]
Serial data input, UART 0.
4
63
I
57
41
I
44
29
I
17
7
I
78
59
I
63
45
I
38
25
I
23
11
I
Data Sheet Revision 1.0
IrDA_In[0:3]
IrDA_In[0:3]
IrDA_In[0:3]
IrDA_In[0:3]
CTS[3]#
CTS[2]#
CTS[1]#
CTS[0]#
UART IrDA data inputs, for each uart respectively.
Serial data input pins redefined as IrDA data inputs when MCR[6] of the
corresponding UART channel is set in enhanced mode
Active-low modem “clear-to-send” input, for each uart respectively.
If automated CTS# flow control is enabled for the corresponding UART
channel, upon deassertion of the CTS# pin, the channel’s transmitter will
complete the current character and enter the idle mode until the CTS# pin
is reasserted. Note: flow control characters are transmitted regardless of
the state of the CTS# pin. The state of this pin is reflected in bit 4 of the
MSR.
It can also be used as a general-purpose input.
Page 11
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