AD8184 Просмотр технического описания (PDF) - Analog Devices

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AD8184

700 MHz, 5 mA 4-to-1 Video Multiplexer

Analog Devices 

AD8184

NOTES

1ENABLE pin is grounded. IN0 and IN2 = +1 V dc, IN1 and IN3 = –1 V dc. A0 is driven with a 0 V to +5 V pulse, A1 is grounded. Measure transition time from 50% of the A0

input value (+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (–1 V), or vice versa. All inputs are measured in a similar

manner using A0 and A1 to select the channels.

2ENABLE pin is driven with 0 V to +5 V pulse (with 3 ns edges). The state of the A0 and A1 pins determines which input is activated (refer to Table I). Set IN0 and IN2 = +1 V dc,

IN1 and IN3 = –1 V dc, and measure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 4, ∆tOFF is the disable time, ∆tON

is the enable time.

3All inputs are grounded. A0 input is driven with 0 V to +5 V pulse, A1 is grounded. The output is monitored. Speeding the edges of the A0 pulse increases the glitch magnitude

due to coupling via the ground plane. Removing the A0 and A1 terminations will lower the glitch, as does increasing RL.

4Decreasing RL slightly lowers the bandwidth. Increasing CL significantly lowers the bandwidth (see Figure 18).

5A resistor (RS) placed in series with the multiplexer inputs serves to optimize 0.1 dB flatness, but is not required (see Figure 19.)

6Select an input that is not being driven (i.e., A0 and A1 are logic 0, IN0 is selected); drive all other inputs with VIN = 0.707 V rms and monitor the output at ƒ = 5 and 30 MHz.

RL = 2 kΩ (see Figure 12).

7Multiplexer is disabled (i.e., ENABLE = logic 1) and all inputs are driven simultaneously with VIN = 0.446 V rms. Output is monitored at ƒ = 5 and 30 MHz. RL = 30 Ω to simu-

late RON of one enabled multiplexer within a system (see Figure 13). In this mode the output impedance is very high (typ 10 MΩ), and the signal couples across the package; the

load impedance determines the crosstalk.

8Voltage gain decreases for lower values of RL. The resistive divider formed by the multiplexers enables output resistance (28 Ω) and RL causes a gain that increases as RL-

decreases (i.e., the voltage gain is approximately 0.97 V/V [3% gain error] for RL = 1 kΩ).

9Larger values of RL provide wider output voltage swings, as well as better gain accuracy. See Note 8.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V

Internal Power Dissipation2

AD8184 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts

AD8184 14-Lead Small Outline (R) . . . . . . . . . . 1.0 Watts

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS

Output Short Circuit Duration . . Observe Power Derating Curves

Storage Temperature Range

N & R Package . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . +300°C

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

2Specification is for device in free air: 14-pin plastic package: θJA = 75°C/Watt

14-pin SOIC package: θJA = 120°C/Watt, where PD = (TJ –TA)/θJA.

ORDERING GUIDE

Model

Temperature Package

Range

Description

Package

Option

AD8184AN

–40°C to +85°C 14-Lead Plastic DIP N-14

AD8184AR

–40°C to +85°C 14-Lead Narrow SOIC R-14

AD8184AR-REEL –40°C to +85°C Reel 14-Lead SOIC R-14

AD8184-EB

Evaluation Board For AD8184R

While the AD8184 is internally short circuit protected, this may

not be sufficient to guarantee that the maximum junction tempera-

ture (+150°C) is not exceeded under all conditions. To ensure

proper operation, it is necessary to observe the maximum power

derating curves shown in Figure 2.

2.5

TJ = +150°C

2.0

14-PIN DIP PACKAGE

1.5

14-PIN SOIC

1.0

0.5

–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

AMBIENT TEMPERATURE – °C

Figure 2. Maximum Power Dissipation vs. Temperature

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8184

is limited by the associated rise in junction temperature. The maxi-

mum safe junction temperature for plastic encapsulated devices is

determined by the glass transition temperature of the plastic,

approximately +150°C. Exceeding this limit temporarily may

cause a shift in parametric performance due to a change in the

stresses exerted on the die by the package. Exceeding a junction

temperature of +175°C for an extended period can result in

device failure.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD8184 feature proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–3–

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