NTE6508 Просмотр технического описания (PDF) - NTE Electronics
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NTE6508 Datasheet PDF : 4 Pages
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Read Cycle Truth Table:
Time Reference
E
–1
H
0
1
L
2
L
3
4
H
5
Inputs
W
A
X
X
H
V
H
X
H
X
H
X
X
X
H
V
Outputs
D
Q
Function
X
Z Memory Disabled
X
Z Cycle Begins, Addresses are Latched
X
X Output Enables
X
V Output Valid
X
V Read Accomplished
X
Z Prepare for Next Cycle (Same as –1)
X
Z Cycle Ends, Next Cycle Begins (Same as 0)
In the NTE6508 Read Cycle, the address information is latched into the on chip registers on the falling
edge of E (T = 0). Minimum address setup and hold time requirements must be met. After the required
hold time, the addresses may change state without affecting device operation. During time (T = 1)
the data output becomes enabled; however, the data is not valid until during time (T = 2). W must
remain high for the read cycle. After the output data has been read, E may return high (T = 3). This
will disable the chip and force the output buffer to a high impedance state. After the required E high
time (TEHEL) the RAM is ready for the next memory cycle (T = 4).
Write Cycle Truth Table:
Time Reference
E
–1
H
0
1
L
2
L
3
4
H
5
Inputs
W
A
X
X
X
V
X
X
H
X
X
X
X
V
Outputs
D
Q
Function
X
Z Memory Disabled
X
Z Cycle Begins, Addresses are Latched
X
Z Write Period Begins
V
Z Data is Written
X
Z Write Completed
X
Z Prepare for Next Cycle (Same as –1)
X
Z Cycle Ends, Next Cycle Begins (Same as 0)
The write cycle is initiated by the falling edge of E which latches the address information into the on
chip registers. The write portion of the cycle is defined as both E and W being low simultaneously.
W may go low anytime during the cycle provided that the write enable pulse setup time (TWLEH) is
met. The write portion of the cycle is terminated by the first rising edge of either E or W. Data setup
and hold times must be referenced to the terminating signal.
If a series of consecutive write cycles are to be performed, the W line may remain low until all desired
locations have been written. When this method is used, data setup and hold times must be referenced
to the rising edge of E. By positioning the W pulse at different times within the E low time (TELEH),
various types of write cycles may be performed.
If the E low time (TELEH) is greater than the W pulse (TWLWH) plus an output enable time (TELQX),
a combination read write cycle is executed. Data may be modified an indefinite number of times dur-
ing any write cycle (TELEH). The data input and data output pins may be tied together for use with
a common I/O data bus structure. When using the RAM in this method allow a minimum of one output
disable time (TWLQZ) after W goes low before applying input data to the bus. This will insure that
the output buffers are not active.
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