NM27C020 Просмотр технического описания (PDF) - Fairchild Semiconductor

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NM27C020

2,097,152-Bit (256K x 8) UV Erasable CMOS EPROM

Fairchild Semiconductor 

Programming Characteristics (Notes 14, 15, 16, 17)

Symbol

tAS

tOES

tCES

tDS

tVPS

tVCS

tAH

tDH

tDF

tPW

tOE

IPP

ICC

TA

VCC

VPP

tFR

VIL

VIH

tIN

tOUT

Parameter

Address Setup Time

OE Setup Time

CE Setup Time

Data Setup Time

VPP Setup Time

VCC Setup Time

Address Hold Time

Data Hold Time

Output Enable to Output

Float Delay

Program Pulse Width

Data Valid from OE

VPP Supply Current during

Programming Pulse

VCC Supply Current

Temperature Ambient

Power Supply Voltage

Programming Supply Voltage

Input Rise, Fall Time

Input Low Voltage

Input High Voltage

Input Timing Reference Voltage

Output Timing Reference Voltage

Condition

OE = VIH

CE = VIL

CE = VIL

CE = VIL

PGM = VIL

Min

1

1

1

1

1

1

0

1

0

45

20

6.25

12.5

5

2.4

0.8

0.8

Typ

50

25

6.5

12.75

0.0

4.0

Max

60

105

100

15

20

30

6.75

13.0

0.45

2.0

2.0

Units

µs

µs

µs

µs

µs

µs

µs

µs

ns

µs

ns

mA

mA

°C

V

V

ns

V

V

V

V

Note 14: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.

Note 15: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with

voltage applied to VPP or VCC.

Note 16: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to

prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients

which may damage the device.

Note 17: During power up the PGM pin must be brought high (≥V IH ) either coincident with or before power is applied to V PP .

7

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