NL6448BC33-54 Просмотр технического описания (PDF) - NEC => Renesas Technology

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NL6448BC33-54

TFT COLOR LCD MODULE

NEC => Renesas Technology 

4.4 POWER SUPPLY VOLTAGE SEQUENCE

4.4.1 Sequence for LCD panel signal processing board

VCC

Note1

3.0V or 4.75V

0V

Display and

function signals

Note2

ON

Tr < 30ms

0ms < t < 35ms

VALID period

NL6448BC33-54

OFF

Toff > 50ms

0ms < t < 35ms

Note1: In terms of voltage variation (voltage drop) while VCC rising edge is below 3.0V in

"VCC = 3.3V" or 4.75V in "VCC = 5.0V", a protection circuit may work, and then this

product may not work.

Note2: Display (CLK, Hsync, Vsync, DE, R0 to R5, G0 to G5, B0 to B5) and function (DPS)

signal must be Low or High-impedance, exclude the VALID period (See above sequence

diagram), in order to avoid that internal circuits is damaged.

If some of display and function signals of this product are cut while this product is

working, even if the signal input to it once again, it might not work normally. If customer

stops the display and function signals, they should be cut VCC.

4.4.2 Sequence for backlight inverter (Option)

Display and

function signals

Note1

Note2

VALID period

VDDB

Note1: These are the display and function signals for LCD panel signal processing board.

Note2: The backlight inverter voltage (VDDB) should be inputted within the valid period of

display and function signals, in order to avoid unstable data display.

DATA SHEET DOD-PD-0072 (2nd edition)

11

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