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NJU26100

NJU26100 Series Hardware Specification

Japan Radio Corporation  

NJU26100 Series

NJU26100 Series Hardware Specification

■ General Description

■Package

This document describes the NJU26100 Series common hardware specifications.

This document is applied to the NJU26101 up to the NJU26199.

The individual function is described in the each data sheet. Please refer to the

each data sheet to find the detail functions. The firmware commands are

described in the each firmware document.

■ Hardware Specification

NJU26100 Series

• 24bit Fixed-point Digital Signal Processing

• Maximum System Clock Frequency

: 38MHz

• Digital Audio Interface

: 3 Input ports / 3 Output ports

• Master / Slave Mode

• Master Mode MCK

:1/2 fclk, 1/3 fclk

ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3)

• Two kinds of micro computer interface

I2C bus (standard-mode/100kbps)

Serial interface (4 lines: clock, enable, input data, output data)

• Power Supply

: 2.5V ( 3.3V Input tolerant )

• Package

: QFP32-R1

at fclk=768Fs

AD1/SDIN AD2/SSb

NJU26100 Series

SCL/SCK

SDA/SDOUT

RESETb

MCK

XI

XO

SERIAL

HOST

INTERFACE

DSP ARITHMETIC UNIT

PROGRAM

CONTROL

ALU

24-BIT x 24-BIT

MULTIPLIER

TIMING

GENERATOR

ADDRESS GENERATION UNIT

SERIAL AUDIO

INTERFACE

SERIAL OUT

SERIAL OUT

SERIAL OUT

SERIAL IN

SERIAL IN

SERIAL IN

BCKO

LRO

SDO0

SDO1

SDO2

SDI0

SDI1

SDI2

BCKI

LRI

DELAY

RAM

DATA

RAM

FIRMWARE

ROM

GPIO AND

CONFIGURATION

INTERFACE

GPIO0

GPIO1

Ver.2005-02-24

-1-

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