NJ88C24 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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NJ88C24 Datasheet PDF : 6 Pages
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NJ88C24
ELECTRICAL CHARACTERISTICS AT VDD = 5V
Test conditions unless otherwise stated:
VDD–VSS=5V ±0·5V. Temperature range = –40°C to +85°C
DC Characteristics
Characteristic
Value
Min. Typ. Max.
Units
Conditions
Supply current
Modulus Control Output (MC)
High level
Low level
Lock Detect Output (LD)
Low level
Open drain pull-up voltage
PDB Output
High level
Low level
3-state leakage current
AC Characteristics
Characteristic
5·5
mA
1.5
mA
fosc, fFIN = 10MHz
fosc, fFIN = 1MHz
0 to 5V
square
wave
4·6
V
ISOURCE = 1mA
0·4
V
ISINK = 1mA
0·4
V
7·0
V
ISINK = 4mA
4·6
V
ISOURCE = 5mA
0·4
V
ISINK = 5mA
±0·1 µA
Value
Min. Typ. Max.
Units
Conditions
FIN and OSC IN input level
Max. operating frequency, fFIN and fosc
Propagation delay, clock to modulus control MC
Programming Inputs
Clock high time, tCH
Clock low time, tCL
Enable set-up time, tES
Enable hold time, tEH
Data set-up time, tDS
Data hold time, tDH
Clock rise and fall times
High level threshold
Low level threshold
Hysteresis
Phase Detector
Digital phase detector propagation delay
Gain programming resistor, RB
Hold capacitor, CH
Programming capacitor, CAP
Output resistance, PDA
200
20
30 50
mV RMS
MHz
ns
10MHz AC-coupled sinewave
Input squarewave VDD to VSS,
25°C.
See note 2
0·5
µs
0·5
µs
All timing periods
0·2
tCH
µs
are referenced to
0·2
µs
the negative
0·2
µs
transition of the
0·2
µs
clock waveform
0·2
µs
VDD20·8 V
See note 1
0·8
V
See note 1
1·0
V
See note 1
500
5
1
1
5
ns
kΩ
nF
See note 3
nF
kΩ
NOTES
1. Data, Clock and Enable inputs are high impedance Schmitt buffers without pull-up resistors; they are therefore not TTL compatible.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs.
4. The inputs to the device should be at logic ‘0’ when power is applied if latch-up conditions are to be avoided. This includes the signal/osc.
frequency inputs.
2
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