NJ8821 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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производитель
NJ8821
Zarlink Semiconductor Inc
NJ8821 Datasheet PDF : 8 Pages
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NJ8821
ELECTRICAL CHARACTERISTICS AT VDD = 5V
Test conditions unless otherwise stated:
VDD–VSS=5V ±0·5V. Temperature range NJ8821 BA: –30°C to +70°C; NJ8821MA: –40°C to +85°C
DC Characteristics
Characteristic
Supply current
OUTPUT LEVELS
Modulus Control Output (MC)
High level
Low level
Lock Detect Output (LD)
Low level
Open drain pull-up voltage
PDB Output
High level
Low level
3-state leakage current
Min.
Value
Typ.
3·5
0·7
Max.
5·5
1·5
Units
mA
mA
Conditions
fosc, fFIN = 10MHz
fosc, fFIN = 1·0MHz
0 to 5V
square
wave
4·6
V
ISOURCE = 1mA
0·4
V
ISINK = 1mA
0·4
V
ISINK = 4mA
7
V
4·6
V
ISOURCE = 5mA
0·4
V
ISINK = 5mA
±0·1 µA
INPUT LEVELS
Data Inputs (D0-D3)
High level
Low level
Program Enable Input (PE)
High level
Low level
Data Select Inputs (DS0-DS2)
High level
Low level
AC Characteristics
Characteristic
FIN and OSC IN input level
Max. operating frequency, fFIN and fosc
Propagation delay, clock to MC
Strobe pulse width, tW(ST)
Data set-up time, tDS
Data hold time, tDH
Latch address set-up time, tSE
Latch address hold time, tHE
Digital phase detector propagation delay
Gain programming resistor, RB
Hold capacitor, CH
Output resistance, PDA
Digital phase detector gain
4·25
V TTL compatible
0·4
V See note 1
4·25
V
0·75 V
4·25
V
0·75 V
Min.
200
10·6
2
1
1
1
1
5
Value
Typ. Max.
Units
Conditions
mVRMS 10MHz AC-coupled sinewave
MHz Input squarewave VDD to VSS,
See note 4.
30 50
ns See note 2.
µs
µs
µs
See Fig. 6
µs
µs
500
ns
kΩ See note 3.
1
nF
5
kΩ
0·4
V/Rad
NOTES
1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs, typically.
4. Operation at up to 15MHz is possible with a full logic swing but is not guaranteed.
2
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