SPT7850SCT(1998) Просмотр технического описания (PDF) - Signal Processing Technologies
Номер в каталоге
Компоненты Описание
производитель
SPT7850SCT Datasheet PDF : 12 Pages
| |||
INPUT PROTECTION
CLOCK INPUT
All I/O pads are protected with an on-chip protection circuit
shown in figure 5. This circuit provides ESD robustness to
3.5 kV and prevents latch-up under severe discharge condi-
tions without degrading analog transition times.
Figure 4 - Recommended Input Protection Circuit
The SPT7850 is driven from a single-ended TTL-input clock.
Because the pipelined architecture operates on the rising
edge of the clock input, the device can operate over a wide
range of input clock duty cycles without degrading the dy-
namic performance. The device's sample rate is 1/2 of the
input clock frequency. (See the timing diagram.)
+V
Buffer
D1
47 Ω
D2
AVDD
ADC
DIGITAL OUTPUTS
The digital outputs (D0-D10) are driven by a separate supply
(OVDD) ranging from +3 V to +5 V. This feature makes it
possible to drive the SPT7850's TTL/CMOS-compatible out-
puts with the user's logic system supply. The format of the
output data (D0-D9) is straight binary. (See table III.) The
outputs are latched on the rising edge of CLK. These outputs
can be switched into a tri-state mode by bringing EN high.
-V
D1 = D2 = Hewlett Packard HP5712 or equivalent
Figure 5 - On-Chip Protection Circuit
VDD
120 Ω
Analog
Table III - Output Data Information
ANALOG INPUT
OVERRANGE
D10
OUTPUT CODE
D9-D0
+F.S. + 1/2 LSB
1
11 1111 1111
+F.S. -1/2 LSB
O
11 1111 111Ø
+1/2 F.S.
O
ØØ ØØØØ ØØØØ
+1/2 LSB
O
OO OOOO OOOØ
0.0 V
O
OO OOOO OOOO
(Ø indicates the flickering bit between logic 0 and 1).
OVERRANGE OUTPUT
120 Ω
Pad
The OVERRANGE OUTPUT (D10) is an indication that the
analog input signal has exceeded the positive full scale input
voltage by 1 LSB. When this condition occurs, D10 will switch
to logic 1. All other data outputs (D0 to D9) will remain at
logic 1 as long as D10 remains at logic 1. This feature makes
it possible to include the SPT7850 into higher resolution
systems.
EVALUATION BOARD
POWER SUPPLY SEQUENCING CONSIDERATIONS
All logic inputs should be held low until power to the device
has settled to the specific tolerances. Avoid power decou-
pling networks with large time constants which could delay
VDD power to the device.
The EB7850 Evaluation Board is available to aid designers in
demonstrating the full performance of the SPT7850. This
board includes a reference circuit, clock driver circuit, output
data latches and an on-board reconstruction of the digital
data. An application note describing the operation of this
board as well as information on the testing of the SPT7850 is
also available. Contact the factory for price and availability.
SPT
9
SPT7850
2/10/98
Share Link: 