NDS335N Просмотр технического описания (PDF) - Fairchild Semiconductor
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NDS335N Datasheet PDF : 6 Pages
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July 1996
NDS335N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N -Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other battery powered circuits where fast switching,
and low in-line power loss are needed in a very small outline
surface mount package.
Features
1.7 A, 20 V. RDS(ON) = 0.14 Ω @ VGS= 2.7 V
RDS(ON) = 0.11 Ω @ VGS= 4.5 V.
Industry standard outline SOT-23 surface mount package
using poprietary SuperSOTTM-3 design for superior thermal
and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
________________________________________________________________________________
D
Absolute Maximum Ratings
Symbol Parameter
TA = 25°C unless otherwise noted
VDSS
VGSS
ID
PD
Drain-Source Voltage
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous (Note 1a)
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
(Note 1a)
Thermal Resistance, Junction-to-Case (Note 1)
© 1997 Fairchild Semiconductor Corporation
G
S
NDS335N
20
8
1.7
10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
NDS335 Rev.C
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