NCV7381(2012) Просмотр технического описания (PDF) - ON Semiconductor
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NCV7381 Datasheet PDF : 23 Pages
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NCV7381
ERRN Pin and Status Register
Provided VIO supply is present together with either VBAT
or VCC, the digital output ERRN indicates the state of the
internal “Error” flag when in Normal mode and the state of
the internal “Wake” flag when in Standby, Go−to−Sleep or
Sleep. In Receive−only mode ERRN indicates either the
state of the internal “Error” or the wakeup source (See
Table 6).
The polarity of the indication is reversed – ERRN pin is
pulled Low when the “Error” flag is set. The signaling on pin
ERRN functions in all operating modes.
Table 6. SIGNALING ON ERRN PIN
STBN
EN
High
High
Conditions
−
High
Low
EN has been set to High after previous wakeup
EN has not been set to High after previous wakeup
Low
x
−
Error flag
not set
set
not set
set
x
x
x
x
Wake flag
x
x
x
x
Set local
Set remote
not set
set
ERRN
High
Low
High
Low
High
Low
High
Low
Additionally, a full set of internal bits referred to as status
register can be read through ERRN pin with EN pin used as
a clock signal – the status register content is described in
Table 7 while an example of the read−out waveforms is
shown in Figure 8 and Figure 9. The individual status bits are
channeled to ERRN pin with reversed polarity (if a status bit
is set, ERRN is pulled Low) at the falling edge on EN pin (the
status register starts to be shifted only at the second falling
edge). As long as the EN pin toggling period falls in the
dENSTAT range, the operating mode is not changed and the
read−out continues. As soon as the EN level is stable for
more than dBDModeChange, the read−out is considered as
finished and the operating mode is changed according the
current EN value. At the same time, the status register bits
S4 to S10 are reset provided the particular bits have been
read−out and the corresponding flags are not set any more –
see Table 7. The status register read−out always starts with
bit S0 and the exact number of bits shifted to ERRN during
the read−out is not relevant.
Table 7. STATUS REGISTER
Bit Number
Status Bit Content
Note
S0
Local wakeup flag
reflects directly the corresponding flag
S1
Remote wakeup flag
S2
not used; always High
S3
Power−on status
the status bit is set if the corresponding flag
was set previously (the respective High level of
S4
Bus error status
the flag is latched in its status counter−part)
S5
Thermal shutdown status
S6
Thermal warning status
S7
TxEN Timeout status
S8
VBAT Under−voltage status
S9
VCC Under−voltage status
S10
VIO Under−voltage status
S11
BGE Feedback
Normal mode: BGE pin logical state (Note 3)
Other modes: Low
S12−S15
not used; always Low
S16−S23
S24−S31
Version of the NCV7381 analog part
Version of the NCV7381 digital part
fixed values identifying the production masks
version
3. The BGE pin state is latched during status register read−out at rising edge of the EN pin.
Reset after Finished
Read−out
no
no
yes, if the
corresponding flag is
reset and the bit was
read−out
−
no
no
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